{"title":"微处理器支持外设系列和直接存取测试方法","authors":"E.M. Aleman","doi":"10.1109/EASIC.1990.207970","DOIUrl":null,"url":null,"abstract":"Designs using LSI peripherals could have testability problems when peripheral I/O's are embedded within the design. A designer must contend with both lack of circuit knowledge and time when developing production test programs for new LSI ASIC offerings. This paper will introduce Intel's microprocessor support peripheral family and the direct access test scheme (DAT). The DAT was developed to isolate each peripheral and allow all signals to be controllable and observable from the package pins. Isolating peripherals allows the designer to use the standard duct test programs. Each MSPF cell will be discussed and compared with its standard product equivalent. Built-in test modifications and additions to the peripherals will be outlined. Testability rules and guidelines are included.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"The microprocessor support peripheral family and the direct access test methodology\",\"authors\":\"E.M. Aleman\",\"doi\":\"10.1109/EASIC.1990.207970\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Designs using LSI peripherals could have testability problems when peripheral I/O's are embedded within the design. A designer must contend with both lack of circuit knowledge and time when developing production test programs for new LSI ASIC offerings. This paper will introduce Intel's microprocessor support peripheral family and the direct access test scheme (DAT). The DAT was developed to isolate each peripheral and allow all signals to be controllable and observable from the package pins. Isolating peripherals allows the designer to use the standard duct test programs. Each MSPF cell will be discussed and compared with its standard product equivalent. Built-in test modifications and additions to the peripherals will be outlined. Testability rules and guidelines are included.<<ETX>>\",\"PeriodicalId\":205695,\"journal\":{\"name\":\"[Proceedings] EURO ASIC `90\",\"volume\":\"24 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-05-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[Proceedings] EURO ASIC `90\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EASIC.1990.207970\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[Proceedings] EURO ASIC `90","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EASIC.1990.207970","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The microprocessor support peripheral family and the direct access test methodology
Designs using LSI peripherals could have testability problems when peripheral I/O's are embedded within the design. A designer must contend with both lack of circuit knowledge and time when developing production test programs for new LSI ASIC offerings. This paper will introduce Intel's microprocessor support peripheral family and the direct access test scheme (DAT). The DAT was developed to isolate each peripheral and allow all signals to be controllable and observable from the package pins. Isolating peripherals allows the designer to use the standard duct test programs. Each MSPF cell will be discussed and compared with its standard product equivalent. Built-in test modifications and additions to the peripherals will be outlined. Testability rules and guidelines are included.<>