A design planner including a fast predictive floorplanning tool

Abstract

The design planner presented in this paper starts from a description of a circuit in terms of interconnected blocks which may be hard blocks (macrocells in a library, generated blocks like RAMs, PLAs) or soft blocks usually generated by synthesis tools. The design planner predicts the cost of a circuit in terms of area, yield and other issues (power, consumption, packaging), according to different technologies. A special attention is given to a fast accurate floorplanning prediction. Experiments on real circuits showed a good prediction accuracy.<>