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[Proceedings] EURO ASIC `90最新文献

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Anatem Version-2-A CMOS timing analyzer for static CMOS networks Anatem Version-2-A CMOS时序分析仪用于静态CMOS网络
[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI: 10.1109/EASIC.1990.207968
M. Froidevaux
{"title":"Anatem Version-2-A CMOS timing analyzer for static CMOS networks","authors":"M. Froidevaux","doi":"10.1109/EASIC.1990.207968","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207968","url":null,"abstract":"A new timing analyzer has been developed. It is able to work at the transistor level, to be back-annotated from the layout, to deal with sequential and combinational logic. The physical way to model the internal timing behavior of a gate, (RC)int, and the use of the least square method to fit experimental and theoretical results, leads to a global accuracy between 10-15% when compared to Eldo (HENN85), for circuits up to 400 transistors, including any kind of static CMOS gates. The number of transistors analyzed is between 100-300 per second, result of first importance for a product used in a timing optimization loop.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125462661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Scan design in the Philips ASIC test environment 扫描设计在飞利浦ASIC测试环境下进行
[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI: 10.1109/EASIC.1990.207971
H. Courjon
{"title":"Scan design in the Philips ASIC test environment","authors":"H. Courjon","doi":"10.1109/EASIC.1990.207971","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207971","url":null,"abstract":"Increasingly complex ASICs need Design For Testability (DFT) techniques to by-pass the test bottleneck. Among the most popular is scan test. The Philips ASIC Test Environment (PATE) includes tools and libraries for scan test and gives ASIC designers a natural approach to DFT. The Philips Components software tools AMSAL and SIMTAP provide Automatic Test Pattern Generation (ATPG) and testability analysis. The silicon overhead due to the scan technique is minimized by dedicated scan flip-flops in the Philips Components ASIC libraries. The PATE approach ensures high quality test vectors and predictable development time from design capture to automatic test vector generation. This paper briefly recalls the basics of scan techniques and then shows their integration in PATE. It finishes with a practical example.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"36 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123355944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A hierarchical behavioural description based CAD system 基于分层行为描述的CAD系统
[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI: 10.1109/EASIC.1990.207955
Y. Nakamura, K. Oguri, A. Nagoya, R. Nomura
{"title":"A hierarchical behavioural description based CAD system","authors":"Y. Nakamura, K. Oguri, A. Nagoya, R. Nomura","doi":"10.1109/EASIC.1990.207955","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207955","url":null,"abstract":"Describes the hierarchical behavioral description language called SFL and its processing system. SFL was developed to aid in the design of the hardware functions and behaviors of ASICs composed solely of clock-synchronized circuits. The main features of SFL are as follows: (1) It is not mixed with connection description, but employs only behavioral description (like procedural description in program language), and it provides hierarchical expression of behavioral description. (2) It permits the description of parallel processing operations by adopting a new hardware task concept. And, (3) it is linked with the behavioral simulator, logic synthesizer, and other components of the processing system. After describing SFL in some detail, a brief explanation of its synthesizer and other processing components is provided, along with its application results in the design of some ASICs.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"248 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123028652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A methodology for performance driven data-path compilation 用于性能驱动的数据路径编译的方法
[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI: 10.1109/EASIC.1990.207925
S. Note, F. Catthoor, G. Goossens, H. de Man
{"title":"A methodology for performance driven data-path compilation","authors":"S. Note, F. Catthoor, G. Goossens, H. de Man","doi":"10.1109/EASIC.1990.207925","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207925","url":null,"abstract":"In this paper, a methodology is described for performance driven compilation of data-paths suited for high throughput real time DSP applications. The emphasis lies on the designers point of view, i.e. on the effect of the different performance optimizations, and the sequence in which to apply them. The resulting methodology has been implemented in a tool called Chopin.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115033179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
PDM, the route to instant mixed analog digital ASICs PDM，路由到即时混合模拟数字asic
[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI: 10.1109/EASIC.1990.208030
G. Birchby
{"title":"PDM, the route to instant mixed analog digital ASICs","authors":"G. Birchby","doi":"10.1109/EASIC.1990.208030","DOIUrl":"https://doi.org/10.1109/EASIC.1990.208030","url":null,"abstract":"The Plessey Design Modelling (PDM) system has been devised to enable the rapid development of a mixed analog digital ASIC. PDM is an integrated hardware bench top modelling system. It enables the design engineer to develop and evaluate a mixed analog digital design whilst interacting with the system environment. Design performance can be fully verified before committing to silicon.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133153761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Domain-specific analog/digital integrated circuits in the gate-forest environment 门森林环境中特定领域的模拟/数字集成电路
[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI: 10.1109/EASIC.1990.207920
E. Habekotté, M. Winkler, U. Apel, R. Grube, E. Salten, L. Spaanenburg, B. Hofflinger
{"title":"Domain-specific analog/digital integrated circuits in the gate-forest environment","authors":"E. Habekotté, M. Winkler, U. Apel, R. Grube, E. Salten, L. Spaanenburg, B. Hofflinger","doi":"10.1109/EASIC.1990.207920","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207920","url":null,"abstract":"An innovative concept for domain-specific mixed analog/digital integrated circuits is introduced. Two exemplary ICs are detailed showing how flexible analog circuitry is merged with the customizable digital Gate-Forest to respond to specific multi-client demands. The domains of smart power and analog control are addressed. Direct-write E-beam supports short turn-around prototyping even for environmental conditions that are difficult to simulate. Two chips of 44 mm/sup 2/ have been developed that combine a semicustom core of 2500 equivalent Gate-Forest SOG with analog interfaces for production in a standard 5 V CMOS technology. On the first chip, eight P-channel open-drain 40 V/50 mA output stages are merged with the semicustom core. On the second chip, two types of SAR (Successive-Approximation-Register) A/D-converters have been combined with a Gate-Forest core.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129079460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Silicon-bipolar ASICs for 2.5 Gbit/s systems-designed and implemented both as full custom circuits and as personalized transistor arrays 用于2.5 Gbit/s系统的硅双极asic设计和实现，可作为完全定制电路和个性化晶体管阵列
[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI: 10.1109/EASIC.1990.207918
W. Bambach, R. Derksen, V. Luck, M. Salvasohn, H. Wernz
{"title":"Silicon-bipolar ASICs for 2.5 Gbit/s systems-designed and implemented both as full custom circuits and as personalized transistor arrays","authors":"W. Bambach, R. Derksen, V. Luck, M. Salvasohn, H. Wernz","doi":"10.1109/EASIC.1990.207918","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207918","url":null,"abstract":"Silicon-bipolar ASICs for 2.5 Gbit/s systems were designed and implemented in different ways. A 4:1-multiplexer, a regenerator, and a 1:4-demultiplexer were realized as full custom circuits. In addition, a second regenerator was implemented using a transistor array. The first measurement results are quite satisfactory. All circuits work up to about 3 Gbit/s and the regenerators have an excellent retiming capability. The measured results agree well with the simulated values.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124603496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Latch-up characterization of semicustom using ATE 使用ATE的半定制锁存特性
[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI: 10.1109/EASIC.1990.207985
S. Gaviraghi
{"title":"Latch-up characterization of semicustom using ATE","authors":"S. Gaviraghi","doi":"10.1109/EASIC.1990.207985","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207985","url":null,"abstract":"An ATE approach for latch-up static test is proposed that allows a quick and complete characterization of devices even with a very high pin count. The software tool is described and some results presented.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114521770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
KIM 20: a symbolic RISC microprocessor for embedded advanced control 用于嵌入式高级控制的符号RISC微处理器
[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI: 10.1109/EASIC.1990.207929
J. Heudin
{"title":"KIM 20: a symbolic RISC microprocessor for embedded advanced control","authors":"J. Heudin","doi":"10.1109/EASIC.1990.207929","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207929","url":null,"abstract":"The author describes a new microprocessor architecture designed applying artificial intelligence techniques in complex process control applications. The KIM 20 embedded RISC microprocessor is a first implementation based on a classic CMOS 1.5 micron technology. Firstly the application field is introduced and secondly a technical overview of the architecture is given. Then, he discusses the ASIC tools used during the design. As a conclusion, the author gives performance results and briefly describes the software environment and future extension of this product.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114649300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An ASIC for a transmission modem with an internal processor core 带有内部处理器核心的传输调制解调器专用集成电路
[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI: 10.1109/EASIC.1990.207982
J. Geier, K. Lucke, I. Rudorff, R. Wimmer
{"title":"An ASIC for a transmission modem with an internal processor core","authors":"J. Geier, K. Lucke, I. Rudorff, R. Wimmer","doi":"10.1109/EASIC.1990.207982","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207982","url":null,"abstract":"Describes the integration of an 80C51 microprocessor with three different ASICs, and especially focuses on the design method, which meets the requirements of a very high success rate. The ASIC EDLC (envelope data link controller) is used for a transmission modem. A whole board with new features was implemented in the EDT. Design for testability embedded in the chip is also described.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129311906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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