用于2.5 Gbit/s系统的硅双极asic设计和实现，可作为完全定制电路和个性化晶体管阵列

[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI:10.1109/EASIC.1990.207918

W. Bambach, R. Derksen, V. Luck, M. Salvasohn, H. Wernz

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引用次数: 0

摘要

采用不同的方法设计和实现了用于2.5 Gbit/s系统的硅双极asic。4:1复用器、再生器和1:4解复用器被实现为完整的定制电路。此外，采用晶体管阵列实现了第二个再生器。初步测量结果令人满意。所有电路的工作速率高达3gbit /s，再生器具有出色的重定时能力。实测结果与模拟值吻合较好。

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Silicon-bipolar ASICs for 2.5 Gbit/s systems-designed and implemented both as full custom circuits and as personalized transistor arrays

Silicon-bipolar ASICs for 2.5 Gbit/s systems were designed and implemented in different ways. A 4:1-multiplexer, a regenerator, and a 1:4-demultiplexer were realized as full custom circuits. In addition, a second regenerator was implemented using a transistor array. The first measurement results are quite satisfactory. All circuits work up to about 3 Gbit/s and the regenerators have an excellent retiming capability. The measured results agree well with the simulated values.<>

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[Proceedings] EURO ASIC `90

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