Anatem Version-2-A CMOS timing analyzer for static CMOS networks

Abstract

A new timing analyzer has been developed. It is able to work at the transistor level, to be back-annotated from the layout, to deal with sequential and combinational logic. The physical way to model the internal timing behavior of a gate, (RC)int, and the use of the least square method to fit experimental and theoretical results, leads to a global accuracy between 10-15% when compared to Eldo (HENN85), for circuits up to 400 transistors, including any kind of static CMOS gates. The number of transistors analyzed is between 100-300 per second, result of first importance for a product used in a timing optimization loop.<>