Scan design in the Philips ASIC test environment

Increasingly complex ASICs need Design For Testability (DFT) techniques to by-pass the test bottleneck. Among the most popular is scan test. The Philips ASIC Test Environment (PATE) includes tools and libraries for scan test and gives ASIC designers a natural approach to DFT. The Philips Components software tools AMSAL and SIMTAP provide Automatic Test Pattern Generation (ATPG) and testability analysis. The silicon overhead due to the scan technique is minimized by dedicated scan flip-flops in the Philips Components ASIC libraries. The PATE approach ensures high quality test vectors and predictable development time from design capture to automatic test vector generation. This paper briefly recalls the basics of scan techniques and then shows their integration in PATE. It finishes with a practical example.<>