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2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)最新文献

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A 27 mV output ripple 92% efficiency buck converter using a multi-bit delta-sigma modulator controller and segmented output switch in 180 nm CMOS 采用多比特δ - σ调制器控制器和180nm CMOS分段输出开关的27mv输出纹波92%效率降压变换器
2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2016-12-01 DOI: 10.1109/ICECS.2016.7841149
Saeed Mehrjoo, M. Taherzadeh‐Sani, F. Nabki
{"title":"A 27 mV output ripple 92% efficiency buck converter using a multi-bit delta-sigma modulator controller and segmented output switch in 180 nm CMOS","authors":"Saeed Mehrjoo, M. Taherzadeh‐Sani, F. Nabki","doi":"10.1109/ICECS.2016.7841149","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841149","url":null,"abstract":"In this paper, a DC-DC buck converter using a multi-bit (two-bits) delta-sigma modulator to control segmented output switches of the converter is proposed to enhance its efficiency and improve its output ripple. This converter operates in continuous condition mode (CCM). Here, the two output bits of the modulator control the switching of the main and the supplementary switches. The circuit is simulated in 180 nm CMOS technology and the simulation results show a peak efficiency of 92% for the converter. The output current can reach up to 1.2A and the input voltage range is from 3.6 V to 1.8 V. The output ripple is 19 mV, 23 mV and 27 mV for 1.5 V, 1.8 V and 2 V output voltages, respectively.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130622372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
ECC module optimization for storage transient error-tolerant ASICs 存储暂态容错asic的ECC模块优化
2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2016-12-01 DOI: 10.1109/ICECS.2016.7841184
Keisuke Inoue
{"title":"ECC module optimization for storage transient error-tolerant ASICs","authors":"Keisuke Inoue","doi":"10.1109/ICECS.2016.7841184","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841184","url":null,"abstract":"This paper discusses the transient error problem on Application Specific Integrated Circuit (ASIC). It focuses especially on the storage part (register) of ASIC since the transient error on registers can be quickly propagated to the other part of the system. It proposes a novel Error Correcting Code (ECC)-based high-level synthesis where ECC modules are suitably controlled to maximize the reliability of ASIC with low cost. It also proposes an integer linear programming-based method to minimize the number of ECC modules, and demonstrated examples show the effectiveness of the proposed method.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130872792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Designing CT ΣΔ modulators with www.sigma-delta.de 利用www.sigma-delta.de设计CT ΣΔ调制器
2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2016-12-01 DOI: 10.1109/ICECS.2016.7841232
J. Wagner, M. Ortmanns
{"title":"Designing CT ΣΔ modulators with www.sigma-delta.de","authors":"J. Wagner, M. Ortmanns","doi":"10.1109/ICECS.2016.7841232","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841232","url":null,"abstract":"Due to a high performance and its inherent filtering capabilities, continuous-time (CT) ΣΔ modulators are the state-of-the-art for many different applications. In this demo, it is shown how to use www.sigma-delta.de for the design of these modulators. Moreover, the visitors are assisted to try the tool themselves on their own devices (e.g. notebooks, tablets, smartphones).","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"61 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134594885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Enhanced Arbiter PUFs using custom sized structures for reduced noise sensitivity 增强的仲裁puf使用自定义大小的结构，以降低噪音敏感性
2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2016-12-01 DOI: 10.1109/ICECS.2016.7841265
Andreas Herkle, Markus Schuster, J. Becker, M. Ortmanns
{"title":"Enhanced Arbiter PUFs using custom sized structures for reduced noise sensitivity","authors":"Andreas Herkle, Markus Schuster, J. Becker, M. Ortmanns","doi":"10.1109/ICECS.2016.7841265","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841265","url":null,"abstract":"This paper presents a simple yet effective way of improving delay based Physical Unclonable Functions by changing transistor gate sizes only. All utilized components of an Arbiter PUF were simulated in a 90 nm CMOS process with sweeps applied to each gate dimension. By evaluating an Arbiter PUF consisting of the proposed enhanced components, we show that the intra Hamming distance can be decreased by over 60 % and the inter Hamming distance can be fixed at 50 %.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"381 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133418344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Power-efficient sum of absolute differences architecture using adder compressors 使用加法器压缩器的高能效绝对差和架构
2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2016-12-01 DOI: 10.1109/ICECS.2016.7841202
Bianca Silveira, Guilherme Paim, C. Diniz, E. Costa
{"title":"Power-efficient sum of absolute differences architecture using adder compressors","authors":"Bianca Silveira, Guilherme Paim, C. Diniz, E. Costa","doi":"10.1109/ICECS.2016.7841202","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841202","url":null,"abstract":"The calculation of the Sum of Absolute Differences (SAD) is one of the most time-consuming operations of the video encoder compatible with the new High Efficiency Video Coding (HEVC) standard. SAD hardware architecture employs an adder tree to accumulate the coefficients from absolute difference between two video blocks. This paper proposes the exploration of the different adder compressors structures in the SAD hardware architecture. The architectures were synthesized to 45nm standard cells. Synthesis results show that SAD architecture with adder compressors with Kogge-Stone adders in the recombination line reduces power dissipation in 60.8% on average when compared with SAD architecture using conventional adders from the synthesis tool.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132063659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A smart all-digital charge to digital converter 智能全数字充电到数字转换器
2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2016-12-01 DOI: 10.1109/ICECS.2016.7841290
Yuqing Xu, D. Shang, Fei Xia, A. Yakovlev
{"title":"A smart all-digital charge to digital converter","authors":"Yuqing Xu, D. Shang, Fei Xia, A. Yakovlev","doi":"10.1109/ICECS.2016.7841290","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841290","url":null,"abstract":"Capacitance sensors, that report the values of capacitances as digital codes, are important in such areas as biomedical, environmental, and mobile applications. Voltage sensors are also widely used in many modern application areas, e.g. where battery life information is important. Conventional capacitance sensing methods use complex ADC techniques that are power hungry, and existing digital solutions, which use the charge to digital conversion (CDC) method tend to suffer from slow sensing response. A novel dual-use all-digital CDC method is proposed in this paper, which can be used to sense either capacitance values as a capacitance sensor or voltage levels as a voltage sensor. It shows low power/energy consumption and fast sensing response.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"6 17","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113979425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
FPGA-based lock-in amplifier with sub-ppm resolution working up to 6 MHz 基于fpga的锁相放大器，分辨率低于ppm，工作频率高达6 MHz
2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2016-12-01 DOI: 10.1109/ICECS.2016.7841146
G. Gervasoni, M. Carminati, G. Ferrari
{"title":"FPGA-based lock-in amplifier with sub-ppm resolution working up to 6 MHz","authors":"G. Gervasoni, M. Carminati, G. Ferrari","doi":"10.1109/ICECS.2016.7841146","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841146","url":null,"abstract":"Digital lock-in amplifiers are largely used to perform high-resolution measurements in different scientific fields. The experimental evidence shows that state-of-the-art, high frequency commercial models do not allow to measure signals with a resolution better than few tens of ppm due to additional signal-proportional 1/f noise observed on the lock-in output. This noise arises from low-frequency gain fluctuations experienced by the signal during the path from the generation stage to the acquisition one. To overcome these fluctuations, we conceived and implemented a novel switched ratiometric architecture allowing noise rejection, whose performance has been experimentally verified obtaining a resolution enhancement by more than an order of magnitude (from 9 to 0.6 ppm). The realized mixed-signal board (called ELIA as Enhanced Lock-In Amplifier) is described and some important design details to maximize the resolution of the lock-in amplifier are discussed.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124004345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Application specific image processor for the extension of the dynamic range of images with multiple resolutions 应用特定的图像处理器，用于扩展具有多种分辨率的图像的动态范围
2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2016-12-01 DOI: 10.1109/ICECS.2016.7841298
G. Licciardo, Carmine Cappetta, L. D. Benedetto
{"title":"Application specific image processor for the extension of the dynamic range of images with multiple resolutions","authors":"G. Licciardo, Carmine Cappetta, L. D. Benedetto","doi":"10.1109/ICECS.2016.7841298","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841298","url":null,"abstract":"A new processor is proposed, capable to expand the dynamic range of input images in real-time. With respect to the existent literature, the processor presents the unique feature of elaborating images at different resolutions, up to 4K UHDTV, by deriving a specific algorithm from the most effective methods presented in the literature. Additionally, the proposed design is capable to elaborate the input pixel in streaming order, as they come from input devices by avoiding frame buffers and eliminating external DRAM. The processor complexity can be configured with different area/speed ratios in order to meet the requirements of different FPGA platforms. Implemented on a high-end FPGA the processor exhibits a latency of 32.4ms (31 fps), while a 4K frame requires 129ms (8 fps) to be processed.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129377857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Advanced electronic circuit breaker techniques for the use in electric vehicle charging stations 用于电动汽车充电站的先进电子断路器技术
2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2016-12-01 DOI: 10.1109/ICECS.2016.7841288
I. Stoychev, J. Oehm
{"title":"Advanced electronic circuit breaker techniques for the use in electric vehicle charging stations","authors":"I. Stoychev, J. Oehm","doi":"10.1109/ICECS.2016.7841288","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841288","url":null,"abstract":"For a charging process of an electric vehicle it is important that the process runs safely from the view of the electric site. For this reason in this paper advanced electronic circuit breaker techniques are presented, optimised for the use in electric vehicle charging stations. In doing so the focus lies on the continuous monitoring of the charging process related to the temporal course of the voltage and current readings. Therefore especially algorithms for the detection of the steady state are proposed, which are to be applied at the beginning of charging processes. Several trigger mechanisms for the circuit breaker have to be implemented on an FPGA board, which amongst other things does the signal processing for energy measurement purpose, too. In general the usage of an FPGA as a central part of the charging station provides wide flexibility in configuration from various viewpoints. That is why the proposed trigger algorithms for the circuit breakers can be parameterised easily, and if needed changed. By implementing the proposed circuit breaker techniques there are no significant additional costs for the system, because typically all necessary components are available within an electric vehicle charging station.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128670620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Noise analysis of current mode differential integrators 电流模式差分积分器的噪声分析
2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2016-12-01 DOI: 10.1109/ICECS.2016.7841151
Hikmet Çeliker, Günhan Dündar
{"title":"Noise analysis of current mode differential integrators","authors":"Hikmet Çeliker, Günhan Dündar","doi":"10.1109/ICECS.2016.7841151","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841151","url":null,"abstract":"A detailed noise analysis for current-mode differential integrators is presented. Feedback analysis is performed and compared with simulations made on MENTOR ELDO using UMC 130nm technology process. Simulation results are presented verifying theoretical results. The effect of enhancing DC-gain of the integrator on the noise is examined. It is concluded that the positive feedback in the current-mode integrator circuit causes high noise levels.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117217238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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