ECC module optimization for storage transient error-tolerant ASICs

Abstract

This paper discusses the transient error problem on Application Specific Integrated Circuit (ASIC). It focuses especially on the storage part (register) of ASIC since the transient error on registers can be quickly propagated to the other part of the system. It proposes a novel Error Correcting Code (ECC)-based high-level synthesis where ECC modules are suitably controlled to maximize the reliability of ASIC with low cost. It also proposes an integer linear programming-based method to minimize the number of ECC modules, and demonstrated examples show the effectiveness of the proposed method.