Power-efficient sum of absolute differences architecture using adder compressors

The calculation of the Sum of Absolute Differences (SAD) is one of the most time-consuming operations of the video encoder compatible with the new High Efficiency Video Coding (HEVC) standard. SAD hardware architecture employs an adder tree to accumulate the coefficients from absolute difference between two video blocks. This paper proposes the exploration of the different adder compressors structures in the SAD hardware architecture. The architectures were synthesized to 45nm standard cells. Synthesis results show that SAD architecture with adder compressors with Kogge-Stone adders in the recombination line reduces power dissipation in 60.8% on average when compared with SAD architecture using conventional adders from the synthesis tool.