FPGA-based lock-in amplifier with sub-ppm resolution working up to 6 MHz

Abstract

Digital lock-in amplifiers are largely used to perform high-resolution measurements in different scientific fields. The experimental evidence shows that state-of-the-art, high frequency commercial models do not allow to measure signals with a resolution better than few tens of ppm due to additional signal-proportional 1/f noise observed on the lock-in output. This noise arises from low-frequency gain fluctuations experienced by the signal during the path from the generation stage to the acquisition one. To overcome these fluctuations, we conceived and implemented a novel switched ratiometric architecture allowing noise rejection, whose performance has been experimentally verified obtaining a resolution enhancement by more than an order of magnitude (from 9 to 0.6 ppm). The realized mixed-signal board (called ELIA as Enhanced Lock-In Amplifier) is described and some important design details to maximize the resolution of the lock-in amplifier are discussed.