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2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)最新文献

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An low-energy 8T dual-port SRAM for image processor with selective sourceline drive scheme in 28-nm FD-SOI process technology 采用28nm FD-SOI制程技术的低功耗8T双端口SRAM图像处理器，具有选择性源端驱动方案
2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2016-12-01 DOI: 10.1109/ICECS.2016.7841256
Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Y. Kawamoto, Kenta Takagi, S. Yoshimoto, S. Izumi, H. Kawaguchi, M. Yoshimoto
{"title":"An low-energy 8T dual-port SRAM for image processor with selective sourceline drive scheme in 28-nm FD-SOI process technology","authors":"Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Y. Kawamoto, Kenta Takagi, S. Yoshimoto, S. Izumi, H. Kawaguchi, M. Yoshimoto","doi":"10.1109/ICECS.2016.7841256","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841256","url":null,"abstract":"This paper presents a low-energy and low-voltage 64-kb 8T dual-port image memory in a 28-nm FD-SOI process technology. Our proposed SRAM adopts the selective sourceline drive (SSD) scheme and the consecutive data write technique for improving active energy efficiency at the low voltage. We fabricated a 64-Kb 8T dual-port SRAM in the 28-nm FD-SOI process technology; the test chip exhibits 0.48 V operation and an access time of 135 ns. The energy minimum point is at a supply voltage of 0.56 V and an access time of 35 ns, where 265.0 fJ/cycle in write operation and 389.6 fJ/cycle in read operation are achieved; these factors are 30% and 26% smaller than those in the 8T dual-port SRAM with the conventional selective sourceline control (SSLC) scheme, respectively.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128556687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 25Gb/s low-noise optical receiver in 0.13 μm SiGe BiCMOS 一种0.13 μm SiGe BiCMOS的25Gb/s低噪声光接收机
2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2016-12-01 DOI: 10.1109/ICECS.2016.7841267
Dan Li, Zimou Zhang, Yang Xie, Ming Liu, Qian Yang, Li Geng
{"title":"A 25Gb/s low-noise optical receiver in 0.13 μm SiGe BiCMOS","authors":"Dan Li, Zimou Zhang, Yang Xie, Ming Liu, Qian Yang, Li Geng","doi":"10.1109/ICECS.2016.7841267","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841267","url":null,"abstract":"A 25Gb/s CMOS optical receiver with superior noise performance is presented. The fully integrated receiver comprises a transimpedance amplifier (TIA), a main amplifier (MA), auxiliary analog loops and on-chip bias circuitry. The receiver employs a novel noise optimization technique for BJT-based shunt-feedback TIA, together with gain and bandwidth boosting methods to achieve low noise. Designed and implemented in 0.13μm SiGe BiCMOS technology and intended to interface a commercial photodiode, the receiver demonstrates state-of-the-art input-referred noise current of 1.66μArms, reveals 78dB transimpedance gain and 18.6GHz bandwidth while consuming 96mW.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130061425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
RF energy harvesting chip powered sensor node 射频能量采集芯片供电的传感器节点
2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2016-12-01 DOI: 10.1109/ICECS.2016.7841310
Younus Syed, B. G. Hegde, T. Prabhakar, M. Manjunath, K. Vinoy
{"title":"RF energy harvesting chip powered sensor node","authors":"Younus Syed, B. G. Hegde, T. Prabhakar, M. Manjunath, K. Vinoy","doi":"10.1109/ICECS.2016.7841310","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841310","url":null,"abstract":"This work demonstrates a BLE compatible battery-less Wireless Sensor Mote, powered by an RF Energy Harvesting (RFEH) Chip. The chip integrates Energy Harvesting and Power conditioning circuits. RF-Energy is harvested from UHF RFID receiver (i.e, 865–868 MHz) and is stored in an external capacitor bank. This energy is utilized to run a microcontroller + radio SoC, wherein data from a sensor (analog temperature sensor) is read and broadcasted as BLE advertisement packets. An android app was developed to process and display the sensor value. The designed chip harvests at power level of −12 dBm and above. Whereas the complete system works at a power level of −8dbm. The maximum BLE packet transmission interval at the specified power level is about 30 minutes. To the best of our knowledge, this is the first work to demonstrate BLE broadcast with RF Harvesting.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"241 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130065814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
K-band SiGe dual-input LNA and detector for SoC radiometers for remote sensing of atmosphere k波段SiGe双输入LNA和用于大气遥感SoC辐射计的探测器
2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2016-12-01 DOI: 10.1109/ICECS.2016.7841200
L. Aluigi, D. Pepe, D. Zito
{"title":"K-band SiGe dual-input LNA and detector for SoC radiometers for remote sensing of atmosphere","authors":"L. Aluigi, D. Pepe, D. Zito","doi":"10.1109/ICECS.2016.7841200","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841200","url":null,"abstract":"SoC miniaturization of radiometric sensors could dramatically improve quantitatively the study of Earth's atmosphere in the microwave and millimeter-wave frequency spectrum, enabling cost and weight reductions both for ground- and space-based observation instruments. This paper reports the K-band silicon-germanium (SiGe) dual-input low noise amplifier (DILNA) and detector designed for the system-on-chip (SoC) Dicke radiometers, and the results of their experimental characterization. The DILNA exhibits power gain close to 16 dB and noise figure close to 6 dB at 24 GHz. The power consumption amounts to 21.9 mW. The detector exhibits a responsivity of 28.1 kV/W and a noise equivalent power (NEP) of 3.1 pW/VHz. The system analysis of the SoC Dicke radiometer incorporating the fabricated DILNA and detector shows that a resolution of 1 K can be achieved with reasonable integration time (14.5 s).","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122347155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
PVT variability analysis of FinFET and CMOS XOR circuits at 16nm 16nm下FinFET和CMOS XOR电路的PVT变异性分析
2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2016-12-01 DOI: 10.1109/ICECS.2016.7841255
F. A. D. Silva, P. Butzen, C. Meinhardt
{"title":"PVT variability analysis of FinFET and CMOS XOR circuits at 16nm","authors":"F. A. D. Silva, P. Butzen, C. Meinhardt","doi":"10.1109/ICECS.2016.7841255","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841255","url":null,"abstract":"This work compares many different transistors arrangements of XOR logic gates under PVT variability effect in 16nm device technologies: CMOS Bulk and FinFET. The objective is to identify how these two different device technologies deal with PVT variability effects on performance and power characteristics. Ten different XOR topologies are evaluated. The results show different transistor arrangements have distinct behavior under PVT variability. FinFET technology show better delay results for PVT variation. CMOS Bulk technology obtained better robustness in power analysis. Considering the different conditions that the integrated circuits are submitted, the results provide valuable data and show that the impact of variability is an important factor that has to be explored to design more robust circuits in the most appropriated technology.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116522801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A continuous-time field programmable analog array with 1 GHz GBW 一种1ghz / GBW的连续现场可编程模拟阵列
2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2016-12-01 DOI: 10.1109/ICECS.2016.7841169
J. Becker, J. Anders, M. Ortmanns
{"title":"A continuous-time field programmable analog array with 1 GHz GBW","authors":"J. Becker, J. Anders, M. Ortmanns","doi":"10.1109/ICECS.2016.7841169","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841169","url":null,"abstract":"This paper presents a vastly reconfigurable Field Programmable Analog Array (FPAA) for the instantiation of continuous-time (CT) analog filters up to 7th order. The circuit manufactured in a 90 nm CMOS technology contains 55 digitally tunable Gm-cells connected in a hexagonal network topology. Each Gm-cell is coarsely tunable by parallel connection of 1 to 6 unit-OTAs and smoothly tunable by a very area efficient 10 bit charge redistribution DAC adjusting the bias current. The Gm-cell corner frequency can be set to exceed 1 GHz bandwidth, which allows a huge amount of reconfigurable filters with almost continuously tunable corner frequencies from below 1 MHz to beyond 1 GHz.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"251 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124158620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Cell-aware MBFF utilization for clock power reduction 降低时钟功耗的蜂窝感知MBFF利用率
2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2016-12-01 DOI: 10.1109/ICECS.2016.7841285
Jin-Tai Yan, Meng-Tian Chen, Chia-Heng Yen
{"title":"Cell-aware MBFF utilization for clock power reduction","authors":"Jin-Tai Yan, Meng-Tian Chen, Chia-Heng Yen","doi":"10.1109/ICECS.2016.7841285","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841285","url":null,"abstract":"Utilization of multi-bit flip-flops(MBFFs) in a synchronous design has been becoming a significant methodology for clock power reduction. In this paper, given a synchronous system with a set of 1-bit flip-flops in a placement plane, the timing constraints of the associated signals on the flip-flops and the available MBFFs in a cell library, firstly, based on the timing constraints of the signals on the flip-flops, a timing-constrained merging graph(TCMG) can be constructed. Furthermore, based on the available MBFFs in the given cell library, an ILP(Integer-Linear-Programming) formulation can be proposed to merge 1-bit flip-flops into the available MBFFs for clock power reduction. Compared with the original design, the experimental results show that our proposed ILP-based approach can reduce 20.05% of the clock power for five tested examples on the average.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126431449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Efficient passive energy harvesters at 950 MHz and 2.45 GHz for 100 μW applications in 65 nm CMOS 950 MHz和2.45 GHz的高效无源能量采集器，适用于65 nm CMOS中100 μW的应用
2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2016-12-01 DOI: 10.1109/ICECS.2016.7841250
Pierre-Antoine Haddad, J. Raskin, D. Flandre
{"title":"Efficient passive energy harvesters at 950 MHz and 2.45 GHz for 100 μW applications in 65 nm CMOS","authors":"Pierre-Antoine Haddad, J. Raskin, D. Flandre","doi":"10.1109/ICECS.2016.7841250","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841250","url":null,"abstract":"Two 2-stage rectifiers are designed at 950 MHz and 2.45 GHz in 65 nm CMOS bulk technology to provide a 100 μW output power under 1 V with 79.9% and 76.6% power conversion efficiency, respectively. A portable and automated design methodology is used here based on foundry models. This methodology is extended to optimize both the cross-coupled and differentialdrive rectifier architectures at UHF by using a derivative-free optimization algorithm. Transistor and capacitance sizing are discussed based on the method results and a simple RC-filter model. A first-order matching network is used to simulate the overall conversion efficiency of an energy-harvesting system using a 50 Ω antenna. For 100 μW output power, minimum input powers of −8.84 dBm and −8.56 dBm are simulated at 950 MHz and 2.45 GHz, respectively. These low power and high-efficiency AC/DC power converters can be used as energy harvesters in RF links to power wearable biomedical devices.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127849312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Energy efficient bootstrapped CMOS inverter for ultra-low power applications 超低功耗应用的高能效自启动CMOS逆变器
2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2016-12-01 DOI: 10.1109/ICECS.2016.7841252
Mohammed Al-daloo, A. Yakovlev, Basel Halak
{"title":"Energy efficient bootstrapped CMOS inverter for ultra-low power applications","authors":"Mohammed Al-daloo, A. Yakovlev, Basel Halak","doi":"10.1109/ICECS.2016.7841252","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841252","url":null,"abstract":"This paper describes an energy efficient boot-strapped CMOS inverter for ultra-low power applications. The proposed design is achieved by internally boosting the gate voltage of the transistors (via the charge pumping technique), and the operating region is shifted from the sub-threshold to a higher region, enhancing performance and improving tolerance to PVT variations. Despite the proposed bootstrapped driver operates with a sub-threshold power supply it uses fewer transistors engaging in this region by utilizing two stages. The first stage is a normal driver with PMOS and NMOS transistors that are driven by the enhancing voltage circuit (stage 2) which generates voltage levels theoretically between −VDD for pulling up to 2Vdd for pulling down. Our analysis shows that the proposed implementation achieves around 20% reduction in energy consumption compared to conventional designs under a supply voltage of 0.15V VDD.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"231 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129112532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 2-Gb/s 60 GHz transmission-gate based 130nm CMOS on-off keying modulator 一种基于2gb /s 60ghz传输门的130nm CMOS开关键控调制器
2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2016-12-01 DOI: 10.1109/ICECS.2016.7841222
N. Sarimin, Rahma Abdaoui, C. Anghel
{"title":"A 2-Gb/s 60 GHz transmission-gate based 130nm CMOS on-off keying modulator","authors":"N. Sarimin, Rahma Abdaoui, C. Anghel","doi":"10.1109/ICECS.2016.7841222","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841222","url":null,"abstract":"A 2-Gb/s 60GHz On-Off Keying modulator for low-power and high-speed applications is demonstrated in this paper. The modulator uses a transmission-gate to selectively block or pass the input signal. Overall, the modulator circuit achieves a maximum data rate of 2-Gb/s, 20dB On and Off isolation, and power consumption of 13.2mW for a supply voltage of 1.2V.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130443676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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