Cell-aware MBFF utilization for clock power reduction

Utilization of multi-bit flip-flops(MBFFs) in a synchronous design has been becoming a significant methodology for clock power reduction. In this paper, given a synchronous system with a set of 1-bit flip-flops in a placement plane, the timing constraints of the associated signals on the flip-flops and the available MBFFs in a cell library, firstly, based on the timing constraints of the signals on the flip-flops, a timing-constrained merging graph(TCMG) can be constructed. Furthermore, based on the available MBFFs in the given cell library, an ILP(Integer-Linear-Programming) formulation can be proposed to merge 1-bit flip-flops into the available MBFFs for clock power reduction. Compared with the original design, the experimental results show that our proposed ILP-based approach can reduce 20.05% of the clock power for five tested examples on the average.