PVT variability analysis of FinFET and CMOS XOR circuits at 16nm

This work compares many different transistors arrangements of XOR logic gates under PVT variability effect in 16nm device technologies: CMOS Bulk and FinFET. The objective is to identify how these two different device technologies deal with PVT variability effects on performance and power characteristics. Ten different XOR topologies are evaluated. The results show different transistor arrangements have distinct behavior under PVT variability. FinFET technology show better delay results for PVT variation. CMOS Bulk technology obtained better robustness in power analysis. Considering the different conditions that the integrated circuits are submitted, the results provide valuable data and show that the impact of variability is an important factor that has to be explored to design more robust circuits in the most appropriated technology.