Enhanced Arbiter PUFs using custom sized structures for reduced noise sensitivity

Abstract

This paper presents a simple yet effective way of improving delay based Physical Unclonable Functions by changing transistor gate sizes only. All utilized components of an Arbiter PUF were simulated in a 90 nm CMOS process with sweeps applied to each gate dimension. By evaluating an Arbiter PUF consisting of the proposed enhanced components, we show that the intra Hamming distance can be decreased by over 60 % and the inter Hamming distance can be fixed at 50 %.