{"title":"A 400 Mbps radiation hardened by design LVDS compliant driver and receiver","authors":"G. A. Graceffa, U. Gatti, C. Calligaro","doi":"10.1109/ICECS.2016.7841144","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841144","url":null,"abstract":"A Radiation Hardened By Design (RHBD) LVDS driver and receiver are designed and simulated in a standard 150 nm CMOS technology. The driver and receiver can reach data rates up to 400 Mbps, with respective power consumptions of 15 mW and 12.5 mW from a single 3.3 V power supply. The driver makes use of a standard H-bridge topology, while the receiver consists of the cascade of two stages, a preamplifier and a positive feedback comparator. RHBD is implemented using ELT transistors for Total Ionizing Dose (TID) effects mitigation up to 300 krad and guard-rings to minimize the probability of a Single Event Latchup (SEL). The final test chip contains two drivers and two receivers, with their relative bandgap circuitries, and it has an overall area of 1.913 mm2. Post layout simulation results show complete compatibility of the driver and the receiver with the LVDS standard.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123862588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Cataldo, Guilherme Korol, Ramon Fernandes, G. Sanchez, D. Matos, C. Marcon
{"title":"Evaluation of emerging TSV-enabled main memories on the PARSEC benchmark","authors":"R. Cataldo, Guilherme Korol, Ramon Fernandes, G. Sanchez, D. Matos, C. Marcon","doi":"10.1109/ICECS.2016.7841219","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841219","url":null,"abstract":"This paper evaluates emerging TSV-interconnected memory technologies employed as the main memory of 3D Symmetric MultiProcessing (SMP). As the target architecture, we implemented a typical 3D SMP including L1 and L2 caches together with some tiers of main memory. Besides, we employed DDR3 as a baseline comparison to normalize all results. The experimental results show a tradeoff between energy efficiency and execution time when using six memory technologies executing a set of applications of PARSEC benchmark on Gem5. All evaluated memories reveal significant reductions in energy consumption with some penalization on the execution time. Additionally, HBM shows to be the most promising one, reducing more than five times the energy consumption and giving a small performance boost than DDR3, in general.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123874949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Neural network based on parametrically-pumped oscillators","authors":"G. Csaba, T. Ytterdal, W. Porod","doi":"10.1109/ICECS.2016.7841128","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841128","url":null,"abstract":"We demonstrate that sub-harmonic injection locked oscillators (SHILOs) can serve as building blocks of neural networks. After numerically studying the locking properties of injection-locked ring-oscillator models, we show that resistively or capacitively interconnected networks of such oscillators fall into well-defined ground states, which ground states, in turn, depend on the strength of interconnections. We argue that these networks may serve as efficient hardware implementations for emerging neural network-based processing devices.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123678939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Strain reliability and substrate specific features of passive UHF RFID textile tag antennas","authors":"J. Virkki, T. Björninen, M. Akbari, L. Ukkonen","doi":"10.1109/ICECS.2016.7841218","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841218","url":null,"abstract":"We investigate the strain reliability of passive UHF RFID tags based on antennas printed on two structurally dissimilar textiles. The performance of the tags under strain and during repeated stretching cycles is evaluated through wireless measurements. Initially, both tags achieve read ranges of 9.5 meters and retain high readable ranges under notable, 20%, strain. Our results from a cyclic strain test evidence that the fabric substrate structure and elasticity play an important role in the reliability and recovery of printed thick-film conductors.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120946499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Enhanced voltage buffer compensation technique for two-stage CMOS operational amplifiers","authors":"R. Zurla, A. Cabrini, M. Pasotti, G. Torelli","doi":"10.1109/ICECS.2016.7841147","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841147","url":null,"abstract":"This paper presents a novel compensation scheme for two-stage CMOS operational amplifiers. The proposed solution is based on voltage-buffer compensation, but uses a gain stage in the feedback compensation path. An additional degree of freedom is introduced and a wider separation of the first two poles is achieved. A compensation procedure is proposed to benefit from these advantages. The proposed compensation technique allows achieving a K-times higher gain-bandwidth product with a K2-times smaller compensation capacitor (where K is the gain of the additional gain stage) with respect to conventional Miller and voltage-buffer compensation. The scheme was analyzed theoretically and simulated in standard 0.35 μm high-voltage CMOS technology. Simulation results show a design where a gain-bandwidth product about 7-times higher was obtained with a compensation capacitor reduced by a factor of about 50.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"208 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114354226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Smart e-Patch for drugs monitoring in schizophrenia","authors":"Tugba Kilic, V. Brunner, L. Audoly, S. Carrara","doi":"10.1109/ICECS.2016.7841131","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841131","url":null,"abstract":"Personalized medicine is experiencing an unprecedented growth in part driven by transformative advances in novel diagnostics tools helping both patients and healthcare professionals with prevention, detection, diagnosis, follow-up, and decision making. t. Biosensors (both implantable and wearable) are an important tool in this space providing direct detection of disease markers and therapeutic drugs. Perspiration analysis offers multiple differentiation opportunities for biosensor design due to the facts that it doesn't require invasive sampling and that mounting evidence to date support the relevance of relevant biomarkers in sweat too. While there is an ongoing research on wearable biosensors for sweat analysis, there is not any report so far on drug detection on the skin. In the present paper, we propose the new idea of a smart e-Patch with integrated electrochemical sensor designed for detection of a novel compound (F17464) developed by Pierre Fabre for the treatment of schizophrenia. This e-Patch is designed for continuous monitoring of drug intake of patients via monitoring of the drug concentration in their perspiration. Our preliminary studies performed to detect this drug in perspiration liquid showed that a direct detection is feasible with a limit of detection of 0.82 μM despite the presence of other electroactive interfering compounds in the perspiration. It is also shown that the designed biosensor is selective for F17464 even when the drug is in presence of a potentially co-administered product (compound B).","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124299891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Geometric variability impact on 7nm Trigate combinational cells","authors":"A. Zimpeck, Y. Aguiar, C. Meinhardt, R. Reis","doi":"10.1109/ICECS.2016.7841119","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841119","url":null,"abstract":"Multigate devices are the main candidates to replace planar devices in the sub 10nm technologies. Besides all advantages, unfortunately, these processes bring additional variability sources due to the 3D channel structure. In this work, the impact of Trigate fin shape variability on the nominal behavior of a set of combinational cells at 7nm is investigated. Results show that, although 5% of geometric deviation have insignificant impact on power and delay, variations over 10% can significantly affects delay and PDP expected behavior of the majority of the circuits evaluated.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124152339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A reliable PPV characterization method for memristor-based oscillators","authors":"Bo Wang, Hanyu Wang, Miao Qi","doi":"10.1109/ICECS.2016.7841127","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841127","url":null,"abstract":"PPV (Perturbation Projection Vector) modeling is an unifying theory for the characterization of the general oscillators. However, for the emerging memristor-based oscillators, the existing PPV abstraction method, which is based on the direct PSS/PXF simulation, encounters the convergence problem due to the hidden state. In this paper we propose a reliable PPV abstraction method based on the conversion from PRC (Phase Response Curve) — a concept from the biological discipline. This conversion method is verified rigorously by transistor-level simulation of Colpitts and ring oscillators circuits. Then we apply the proposed method to the PPV characterization of the memristor-based oscillator, and successfully obtain its PPV from the conversion of PRC.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127834891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Royet, J. Michel, B. Reig, J. Pornin, M. Ranaivoniarivo, B. Robain, Pierre de Person, Gregory Uren
{"title":"Design of optimized high Q inductors on SOI substrates for RF ICs","authors":"A. Royet, J. Michel, B. Reig, J. Pornin, M. Ranaivoniarivo, B. Robain, Pierre de Person, Gregory Uren","doi":"10.1109/ICECS.2016.7841198","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841198","url":null,"abstract":"This paper presents several experimental and simulation results on 130 nm SOI integrated inductors. Measurements and 3D electromagnetic simulations highlight the efficiency of different layout techniques and technological choices to improve the integrated inductor Q factor. We compare a variable-width spiral inductor with a classical spiral inductor keeping the inductance value constant as an essential parameter for RF circuit designers. A 30% Q factor enhancement is achieved for a same size device and same inductance value. The paper will attempt to provide keys to compromise between Q factor optimization and inductor compactness. The influence of the ratio between internal and external width of the coil's turns and the wire space is also examined.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127894014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. L. Ausín, J. Ramos, J. F. Duque-Carrillo, G. Torelli
{"title":"Analysis of non-idealities in parallel-summation logarithmic amplifiers","authors":"J. L. Ausín, J. Ramos, J. F. Duque-Carrillo, G. Torelli","doi":"10.1109/ICECS.2016.7841262","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841262","url":null,"abstract":"CMOS logarithmic amplifiers based on piecewise linear approximation have been usually analyzed and designed by assuming ideal conditions. This paper discusses non-ideal factors in the used components, which play a key role in the performance of high-accuracy logarithmic amplifiers for sensing applications, and shows that the use of simplified mathematical models may lead to wrong conclusions. A gain-mismatch compensation method that enables wide dynamic range and low-power operation is also outlined.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121457290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}