{"title":"Geometric variability impact on 7nm Trigate combinational cells","authors":"A. Zimpeck, Y. Aguiar, C. Meinhardt, R. Reis","doi":"10.1109/ICECS.2016.7841119","DOIUrl":null,"url":null,"abstract":"Multigate devices are the main candidates to replace planar devices in the sub 10nm technologies. Besides all advantages, unfortunately, these processes bring additional variability sources due to the 3D channel structure. In this work, the impact of Trigate fin shape variability on the nominal behavior of a set of combinational cells at 7nm is investigated. Results show that, although 5% of geometric deviation have insignificant impact on power and delay, variations over 10% can significantly affects delay and PDP expected behavior of the majority of the circuits evaluated.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2016.7841119","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
Multigate devices are the main candidates to replace planar devices in the sub 10nm technologies. Besides all advantages, unfortunately, these processes bring additional variability sources due to the 3D channel structure. In this work, the impact of Trigate fin shape variability on the nominal behavior of a set of combinational cells at 7nm is investigated. Results show that, although 5% of geometric deviation have insignificant impact on power and delay, variations over 10% can significantly affects delay and PDP expected behavior of the majority of the circuits evaluated.