{"title":"Ultra low-power MEMS based radios for the IoT","authors":"R. Thirunarayanan, A. Heragu, D. Ruffieux, C. Enz","doi":"10.1109/ICECS.2016.7841173","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841173","url":null,"abstract":"The start-up phase of the radios is responsible for the major energy drain in duty cycled Internet of Things (IoT) nodes. The main source of this energy drain is the long start-up of the loop based frequency synthesizer; especially the crystal oscillator (XO) frequency reference. In order to greatly reduce this energy drain, this paper presents radios based on micromachined Bulk Acoustic Wave (BAW) resonators that have the capability to start in few μs as opposed to ≈ 1 ms start-up of the traditional XO. In addition, these resonators also have a high Quality factor (Q). This results in the oscillators employing these resonators having excellent phase noise, thereby aiding the development of loop-free frequency synthesizers. The high-Q has also been leveraged to make a very good high frequency filter that has been employed in the sub-sampling receiver presented in this paper.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129998680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High-performance bivariate numeric function approximation for hardware-efficient QR-decomposition","authors":"Jochen Rust, Benjamin Knoop, S. Paul","doi":"10.1109/ICECS.2016.7841181","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841181","url":null,"abstract":"High-performance QR-decomposition is a key request in many different application areas, e.g., multi-antenna wireless communication systems. In order to achieve high performance, bivariate numeric function approximations have turned out to be a promising approach, though it has only been marginal considered so far. In this paper we leverage existing QR-decomposition hardware architectures by exploiting a novel and high-performance approximation technique for bivariate, trigonometric functions. An enhanced piecewise segmentation scheme is proposed which will reduce the size of the multiplexer-tree. To value our work, the performance is measured and analyzed, on both the algorithmic and the microelectronic level. The results indicate our approach to be a highly efficient hardware solution for QR-decomposition in modern multi-antenna communication systems.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"31 11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130004850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Maximizing the fundamental period of a dithered digital delta-sigma modulator with constant input","authors":"Hongjia Mo, Xiao Tan, Michael Peter Kennedy","doi":"10.1109/ICECS.2016.7841241","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841241","url":null,"abstract":"A digital delta-sigma modulator (DDSM) with a constant input may produce a periodic output with a small fundamental period, resulting in strong tonal output behavior instead of the classically predicted shaped white quantization noise. Pseudorandom dither generators based on linear feedback shift registers (LFSRs) are widely used to “break up” periodic cycles in DDSMs with constant inputs. Pseudorandom dither signals are themselves periodic and can lead to relatively short output sequences from dithered DDSMs. It has been shown, for a MASH comprising a cascade of first-order sections, that the fundamental period of the output signal depends not only on the input and initial condition of the DDSM but also on the initial state of the LFSR. This work extends the analysis to a larger class of DDSM architectures.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130211270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hazal Yüksel, D. Yang, Zachariah Boynton, Emory Enroth, Thomas Tapen, A. Molnar, A. Apsel
{"title":"Broadly tunable frequency division duplex transceiver: Theory and operation","authors":"Hazal Yüksel, D. Yang, Zachariah Boynton, Emory Enroth, Thomas Tapen, A. Molnar, A. Apsel","doi":"10.1109/ICECS.2016.7841295","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841295","url":null,"abstract":"Software defined radios (SDR) capable of supporting a wide range of legacy and future systems must be compatible with frequency division duplex (FDD) operation. We have recently demonstrated an FDD capable, integrated SDR (SD-FDD) that achieves >25dB isolation of TX and RX across a wide band while supporting high TX power. This transceiver employs an artificial transmission line and frequency selective TX degeneration to meet the various requirements of FDD-SDR. In this paper, this architecture is analyzed and methods to choose and calibrate the complex input weights of the transmitter are derived. The key degeneration parameters are characterized and how they affect noise is described.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134037623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Elkhayat, Stefano Mangiarotti, C. D. Berti, M. Grassi, P. Malcovati, D. Albano, A. Baschirotto
{"title":"Device matching measurements in 28nm technology for high energy physics experiments","authors":"M. Elkhayat, Stefano Mangiarotti, C. D. Berti, M. Grassi, P. Malcovati, D. Albano, A. Baschirotto","doi":"10.1109/ICECS.2016.7841120","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841120","url":null,"abstract":"This work lies within SCALTECH28 project, whose main purpose is to investigate the performance of the 28nm technology in terms of signal processing quality, power consumption, and radiation hardness for applications in instrumentation electronics for particle physics with respect to previous technological generations. An additional target is to experimentally evaluate radiation damage effects on single devices and on full circuits to develop rad-models for simulations. A test chip including elementary device arrays and dedicated read-out circuits has been developed and fully characterized. In particular, a capacitance to frequency converter has been integrated to measure the matching between different capacitors of a programmable array. Experimental results show that matching performance is comparable to previous technologies, making the 28nm technology eligible for analog signal processing in front-end circuits for physical experiments and related data converters. Samples have been sent to irradiation facility for high energy experiments compliance verification.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134205641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Improved winner-take-all circuit for neural network based on frequency-modulated signals","authors":"H. Hikawa","doi":"10.1109/ICECS.2016.7841138","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841138","url":null,"abstract":"This paper proposes a new winner-take-all (WTA) circuit for WTA neural network (WTANN) that is based on frequency modulated signals. WTA finds winner neuron that has the nearest internal weight vector to input vector, and reliable and efficient frequency comparator is required for the implementation of the WTA circuit. This paper proposes a cycle slip detector to estimate frequency difference of the signals. To evaluate the performance of the proposed WTA, VHDL simulation was conducted. Results revealed that accuracy in WTA operation of the proposed method is much better than the previously proposed WTA circuit.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134096894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ghaith Kazma, Ghaith Bany Hamad, O. Mohamed, Y. Savaria
{"title":"Investigating the efficiency and accuracy of a data type reduction technique for soft error analysis","authors":"Ghaith Kazma, Ghaith Bany Hamad, O. Mohamed, Y. Savaria","doi":"10.1109/ICECS.2016.7841185","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841185","url":null,"abstract":"The progressive scaling of semiconductor technologies has led to significant performance improvements in digital designs. However, ultra-deep sub-micron technologies have increased the vulnerability of VLSI designs to soft errors. It is crucial to analyze this vulnerability early in the design process. In this paper we propose a new technique to model, analyze and estimate the propagation of Single Event Upsets (SEUs) in combinational designs at the Register Transfer Level (RTL) using Satisfiability Modulo Theories (SMT). The propagation of SEUs through RTL bit-vector constructs is modeled as a Satisfiability problem using the SMT theory of bit-vectors. Two different analysis techniques, concrete and abstract modeling, are used in order to investigate the efficiency and accuracy of a data type reduction technique for soft error analysis. Concrete modeling uses two versions of the design, one faulty and one fault-free, in order to analyze SEU propagation. Abstract modeling uses data type reduction to evaluate the difference in performance and accuracy over the first method. Experimental results demonstrate that the loss in accuracy due to abstract modeling depends on the design behavior. For example, for some circuits, the loss in accuracy was arround 73%, while for other circuits it was as low as 0.03%. However, abstract modeling allows reducing processing time significantly and an average reduction factor of 3.88 is reported.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134280024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ramy Sharaf, Sherif Hekal, A. A. El-Hameed, A. A. El-Rahman, R. Pokharel
{"title":"A new compact wireless power transfer system using C-shaped printed resonators","authors":"Ramy Sharaf, Sherif Hekal, A. A. El-Hameed, A. A. El-Rahman, R. Pokharel","doi":"10.1109/ICECS.2016.7841197","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841197","url":null,"abstract":"This paper presents a simple and compact design for an efficient short-range wireless power transfer (WPT) system. The proposed design is composed of two identical transmitting (TX) and receiving (RX) substrates. Each substrate has a micro strip feed line and C-shaped edge coupled resonator. A partial ground plane is added under the feeding line to guide the transmitted/received signals. The C-shaped resonator is loaded by chip capacitor for miniaturization. A circuit model has been extracted for verification of the design theory. The proposed design achieves a WPT efficiency of 69% at 1 GHz and a transmission distance of 15mm.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127310393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Sundarasaradula, T. Constandinou, A. Thanachayanont
{"title":"A 6-bit, two-step, successive approximation logarithmic ADC for biomedical applications","authors":"Y. Sundarasaradula, T. Constandinou, A. Thanachayanont","doi":"10.1109/ICECS.2016.7841123","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841123","url":null,"abstract":"This paper presents the design and realization of a novel low-power 6-bit successive approximation logarithmic ADC for biomedical applications. A two-step successive approximation method is proposed to obtain a piecewise-linear approximation of the desired logarithmic transfer function. The proposed ADC has been designed and simulated using process parameters from a standard 0.35 μm 2P4M CMOS technology with a single 1.8 V power supply voltage. Simulation results show that, at a sampling rate of 25 kS/s, the proposed ADC consumes 4.36 μW to 14.6 μW (proportional to input amplitudes). The proposed ADC achieves 18.6 pJ/conversion-step, maximum INL of 0.45 LSB, an ENOB of 4.97-bits, and SNDR of 31.7 dB with 1 V full-scale input range.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133837247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Local congestion and blockage aware routability analysis using adaptive flexible modeling","authors":"A. Ivanov, P. Hallschmid, Zhonghua Zhou","doi":"10.1109/ICECS.2016.7841230","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841230","url":null,"abstract":"Routing congestion is a significant challenge in integrated circuit design due to their ever-growing number of metal layers, the expanding set of design rules and exponential growth in complexity. This increases the need for an accurate congestion estimation methodology — this estimation approach must be fast such that it can be used within tight loops of other algorithms such as placement. An accurate modeling metric is presented in this paper which has the ability to take into account local congestion, design blockages, as well as the impact of routing due to the application progression. Results show that the congestion map is well predicted and matched with that of post-routing. Blockages are avoided in a similar way to that of a typical detailed router.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"241 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114620476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}