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2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)最新文献

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A smart energy extraction interface for electrostatic vibrational energy harvester 一种用于静电振动能量采集器的智能能量提取接口
2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2016-12-01 DOI: 10.1109/ICECS.2016.7841224
M. Bedier, D. Galayko
{"title":"A smart energy extraction interface for electrostatic vibrational energy harvester","authors":"M. Bedier, D. Galayko","doi":"10.1109/ICECS.2016.7841224","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841224","url":null,"abstract":"This paper introduces a low power smart energy extraction interface for electrostatic vibrational energy harvester. The harvesting of energy is achieved through a variable MEMS capacitor transducer accompanied with a conditioning circuit, while the energy extraction is achieved through a mix of high voltage interface and low power control. The energy extraction interface insures maximum energy extraction from the conditioning circuit. The proposed system switching thresholds can be adjusted externally as needed.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123730490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A hardware configurable self-organizing map for real-time color quantization 用于实时颜色量化的硬件可配置自组织映射
2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2016-12-01 DOI: 10.1109/ICECS.2016.7841201
Mehdi Abadi, S. Jovanovic, K. Khalifa, S. Weber, M. Hedi
{"title":"A hardware configurable self-organizing map for real-time color quantization","authors":"Mehdi Abadi, S. Jovanovic, K. Khalifa, S. Weber, M. Hedi","doi":"10.1109/ICECS.2016.7841201","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841201","url":null,"abstract":"Real-time color quantization requires high performances and high configurability. Self-organizing maps (SOMs) are very suited as color quantizers. However, widely used software SOM quantizers are flexible with limited performances, whereas the hardware counterparts lack in flexibility. In this work, we propose a flexible and adaptable real-time hardware implementation of a SOM map applied to color quantization. The proposed architecture allows to find iteratively, for each processed image, the adequate SOM structure providing optimal quality and performances. It is validated on a 16×16 map using 128×128 RGB images. The proposed reconfiguration allows to improve dynamically the PSNR of processed images by changing the structure of the SOM and its time is estimated to 38 clock cycles.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124650497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
System energy analysis for shared memory multiprocessing applications 共享内存多处理应用的系统能量分析
2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2016-12-01 DOI: 10.1109/ICECS.2016.7841318
D. Silveira, S. Bampi, Gabriel B. Moro, E. Cruz, P. Navaux, L. Schnorr
{"title":"System energy analysis for shared memory multiprocessing applications","authors":"D. Silveira, S. Bampi, Gabriel B. Moro, E. Cruz, P. Navaux, L. Schnorr","doi":"10.1109/ICECS.2016.7841318","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841318","url":null,"abstract":"This paper presents a detailed energy consumption analysis, considering the energy consumption related to CPU, cache memory and main memory of parallel applications on a 16-core HPC platform. The correlations between energy consumption, speedup, and execution time are also herein presented. Tests are conducted with the NAS parallel benchmarks using three different measurement tools: i) Perf, for the measurement of hardware cache memory events; ii) CACTI, used to estimate the cache memory energy consumption by access; and iii) PCM, for CPU and DRAM energy consumption estimates. Our results show that the lowest overall energy consumption occurs only when all physical cores are used, reducing by 62%, on average, the total system energy consumption when compared to the sequential version for the execution. Moreover, the cache memories results are even better, achieving a reduction of 80% in most of the cases, despite the increase in cache miss rate generated by the increased number of threads.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125020784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Efficient and fast SOP-based inpainting for neurological signals in resource limited systems 基于sop的资源有限系统中神经信号的高效快速绘制
2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2016-12-01 DOI: 10.1109/ICECS.2016.7841179
Sebastian Schmale, Pascal Seidel, H. Lange, Benjamin Knoop, D. Peters-Drolshagen, S. Paul
{"title":"Efficient and fast SOP-based inpainting for neurological signals in resource limited systems","authors":"Sebastian Schmale, Pascal Seidel, H. Lange, Benjamin Knoop, D. Peters-Drolshagen, S. Paul","doi":"10.1109/ICECS.2016.7841179","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841179","url":null,"abstract":"This work presents fast and efficient patch matching and ordering techniques for a novel inpainting-based compression and reconstruction methodology to continuously monitor neural activity. The mask-based compression is especially relevant for the technical realization of fully implantable neural measurement systems (NMS), because of restrictions regarding area and energy consumption. Novel approaches for decompression significantly reduce the number of computations for the procedure of smooth ordering patches (SOP) by a restricted neighboring search along consistent electrode patterns and by a patch group matching technique. Both combined yields a speed-up of 49.2x compared to an unrestricted patch search. With regard to recovered signal quality and compression of up to 95%, the proposed bridge mask achieves accurate results. The fast inpainting-based processing, including the proposed patch matching and ordering approaches, outperforms compression-focused standard techniques like JPEG and JPEG2000 regarding reconstruction quality of real measured neurological signals at high degrees of data reduction.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128524715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A low power control system for real-time tuning of a hybrid transformer-based receiver 一种用于混合变压器接收机实时调谐的低功耗控制系统
2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2016-12-01 DOI: 10.1109/ICECS.2016.7841199
G. Castellano, D. Caro, A. Strollo, D. Manstretta
{"title":"A low power control system for real-time tuning of a hybrid transformer-based receiver","authors":"G. Castellano, D. Caro, A. Strollo, D. Manstretta","doi":"10.1109/ICECS.2016.7841199","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841199","url":null,"abstract":"This paper presents the analysis and hardware implementation of a low-power control system for a frequency-division duplexing 3G receiver with a tunable on-chip duplexer based on a hybrid-transformer. The maximum transmit-receive isolation exceeds 60dB and is limited by the precision of the on-chip balancing impedance. An optimization algorithm finds the optimal duplexer tuning condition in less than 100μs and a simple tracking algorithm operating in background preserves this condition over time. The algorithms are implemented in a FPGA and require minimal hardware overhead.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129004353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Delta-sigma modulator based spectrum sensing transceiver 基于Delta-sigma调制器的频谱传感收发器
2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2016-12-01 DOI: 10.1109/ICECS.2016.7841233
Tamer Badran, H. Aboushady
{"title":"Delta-sigma modulator based spectrum sensing transceiver","authors":"Tamer Badran, H. Aboushady","doi":"10.1109/ICECS.2016.7841233","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841233","url":null,"abstract":"The demo illustrates the performance of energy detection spectrum sensing. Time domain energy detection will be shown. Spectrum sensing is crucial for Cognitive Radio Transceiver. The original system under-study in my work is based on a Continuous Time RF Delta Sigma modulator, In the demo — to have the whole concept validated using FPGA board — an emulation of the RF delta sigma modulator is used. The emulation is a discrete time low pass delta sigma modulator followed by an upsampler (zero order interpolator) then an upconverter (using image-rejection mixer) to mimic the output of the originally targeted RF Delta Sigma modulator.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132371962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An effective methodology for robust design of monolithic voltage regulators 一种有效的单片稳压器稳健设计方法
2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2016-12-01 DOI: 10.1109/ICECS.2016.7841166
P. Napolitano, K. Kelliher, B. A. Mukhtar, Diarmuid Carey, Owen Cregg
{"title":"An effective methodology for robust design of monolithic voltage regulators","authors":"P. Napolitano, K. Kelliher, B. A. Mukhtar, Diarmuid Carey, Owen Cregg","doi":"10.1109/ICECS.2016.7841166","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841166","url":null,"abstract":"A procedure for the design of fully integrated voltage regulators is proposed in this paper, for applications requiring high levels of reliability and robustness. A sensitivity analysis is presented, showing how variations in the values of the components, used for the compensation, affect the loop transfer function. To mitigate the effect of process variations and uncertainty in the inductances and capacitances of the output filter, a smart programmable compensation scheme is proposed. The described technique has been verified through transistor level simulations, considering a multiphase buck converter, operated at 1.2-MHz switching frequency, supplied by a 5-V input and generating a 1-V regulated output. The regulator has been designed in a 0.25-μm CMOS technology and occupies a layout area of 0.36-mm2. Without loss of generality, the proposed methodology can be extended to other types of dc-dc switching regulators, single-phase or multi-phase in voltage mode.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130884212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
The analysis of multi-phase current feedforward type-III constant on-time control with ultrafast load transient response for voltage regulator modules 稳压模块的多相电流前馈型超快负载瞬态响应恒准时控制分析
2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2016-12-01 DOI: 10.1109/ICECS.2016.7841167
B. AlMukhtar, Paul Harriman, K. Burke
{"title":"The analysis of multi-phase current feedforward type-III constant on-time control with ultrafast load transient response for voltage regulator modules","authors":"B. AlMukhtar, Paul Harriman, K. Burke","doi":"10.1109/ICECS.2016.7841167","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841167","url":null,"abstract":"This paper presents a new method of addressing the constant on time and minimal off time limitation of widely used COT variable frequency control. This is done by means of estimated capacitor current feedforward method. Ultrafast transient response is achieved with a new COT controller reacting much faster to output caps charge and discharge currents following a load transient step. A new output caps current estimator circuit is presented that accurately models a complex output filter network, including effective series inductance. System frequency response with combined output cap current estimator circuit and a type-II error amplifier shows a voltage mode type-III compensator. New compensator enables higher BW with sufficient phase margin limits. Dynamic performance of 4 phase, 3MHz and 16A load step at 3uSec slew rate show superior transient response in both voltage deviation and recovery time. Integrated controller is implemented in a 0.18μm Tower Jazz process. ASIC performance closely matches target design specs.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130954333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Low-power comparator in 65-nm CMOS with reduced delay time 低功耗比较器在65纳米CMOS与减少延迟时间
2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2016-12-01 DOI: 10.1109/ICECS.2016.7841307
Mohammad Tohidi, J. K. Madsen, M. Heck, F. Moradi
{"title":"Low-power comparator in 65-nm CMOS with reduced delay time","authors":"Mohammad Tohidi, J. K. Madsen, M. Heck, F. Moradi","doi":"10.1109/ICECS.2016.7841307","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841307","url":null,"abstract":"In this paper, a high-speed and low-power latched comparator in a 65-nm CMOS process is presented. In our proposed structure, a latched circuit with an adjusted delayed-clock with no static power consumption is added to the conventional latch-type comparator in order to enhance the clock frequency and reduce the power consumption and the delay time. Therefore, the maximum clock frequency of our proposed structure is enhanced from 700 MHz to 1.7 GHz at 0.6 V. Furthermore, at the clock frequency of 700MHz (at 0.6 V), the power consumption and the delay time of our proposed structure have been decreased by 38% and 65% in comparison with the conventional structure, respectively. Also, other advantages of the conventional comparator as high-impedance input and rail-to-rail output swing are kept in the proposed structure. Finally, the Monte Carlo simulations demonstrate that our proposed structure is robust against the effects of mismatches.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130269598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Study of active inductors with suspendance analysis 有源电感的悬架分析研究
2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2016-12-01 DOI: 10.1109/ICECS.2016.7841153
S. Hamedi-Hagh
{"title":"Study of active inductors with suspendance analysis","authors":"S. Hamedi-Hagh","doi":"10.1109/ICECS.2016.7841153","DOIUrl":"https://doi.org/10.1109/ICECS.2016.7841153","url":null,"abstract":"Finding node admittances with suspendance analysis is introduced in this paper. First, all dependent sources in a circuit are transformed to voltage controlled current sources. Second, the circuit determinant is recursively expanded by shunt followed by sequential passive elements in an order that yields the shortest sub-determinant lengths. Third, the contributions of cross coupled sources (if any exist) are added. A four-node active inductor is analyzed and characterized in this paper. Results fully match with those obtained from Spice simulation verifying the effectiveness of suspendance analysis.","PeriodicalId":205556,"journal":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125395818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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