A low power control system for real-time tuning of a hybrid transformer-based receiver

Abstract

This paper presents the analysis and hardware implementation of a low-power control system for a frequency-division duplexing 3G receiver with a tunable on-chip duplexer based on a hybrid-transformer. The maximum transmit-receive isolation exceeds 60dB and is limited by the precision of the on-chip balancing impedance. An optimization algorithm finds the optimal duplexer tuning condition in less than 100μs and a simple tracking algorithm operating in background preserves this condition over time. The algorithms are implemented in a FPGA and require minimal hardware overhead.