Enhanced voltage buffer compensation technique for two-stage CMOS operational amplifiers

Abstract

This paper presents a novel compensation scheme for two-stage CMOS operational amplifiers. The proposed solution is based on voltage-buffer compensation, but uses a gain stage in the feedback compensation path. An additional degree of freedom is introduced and a wider separation of the first two poles is achieved. A compensation procedure is proposed to benefit from these advantages. The proposed compensation technique allows achieving a K-times higher gain-bandwidth product with a K2-times smaller compensation capacitor (where K is the gain of the additional gain stage) with respect to conventional Miller and voltage-buffer compensation. The scheme was analyzed theoretically and simulated in standard 0.35 μm high-voltage CMOS technology. Simulation results show a design where a gain-bandwidth product about 7-times higher was obtained with a compensation capacitor reduced by a factor of about 50.