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Fault Simulation for Dynamic Failures in Analog and Mixed Signal Circuits 模拟和混合信号电路中动态故障的故障仿真
Proceedings Pub Date : 2023-11-12 DOI: 10.31399/asm.cp.istfa2023p0177
Tommaso Melis
{"title":"Fault Simulation for Dynamic Failures in Analog and Mixed Signal Circuits","authors":"Tommaso Melis","doi":"10.31399/asm.cp.istfa2023p0177","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2023p0177","url":null,"abstract":"Abstract The localization of defects that cause dynamic electrical behavior is a constant challenge for failure analysts. Such types of failures are often present in analog circuits, and standard fault isolation techniques are constrained and not always successful. In this paper, we demonstrate a method to exploit industrial fault simulators in conjunction with standard analysis methods to solve analyses in analog circuits. In addition, we will show methods to adapt fault simulation to these dynamic electrical failure modes. Successful fault isolation results from real-world failure analyses of oscillators, which are typical inside analog and mixed-signal circuits.","PeriodicalId":20443,"journal":{"name":"Proceedings","volume":"99 20","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136353482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Implementation of RFID-based Equipment Management System for Failure Analysis Laboratory Equipment 基于rfid的失效分析实验室设备管理系统的实现
Proceedings Pub Date : 2023-11-12 DOI: 10.31399/asm.cp.istfa2023p0117
Acer Jay Castillo, Mark Anthony Acedillo
{"title":"Implementation of RFID-based Equipment Management System for Failure Analysis Laboratory Equipment","authors":"Acer Jay Castillo, Mark Anthony Acedillo","doi":"10.31399/asm.cp.istfa2023p0117","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2023p0117","url":null,"abstract":"Abstract Completion of failure analysis (FA) cases require a lot of expensive equipment and tools. Equipment Management System (EMS) is a must to safeguard the equipment from being down/damaged due to uncertified/untrained and high number of users and to avoid high repair cost of the FA laboratory equipment. The purpose of this paper is to present the RFID-based equipment management system for failure analysis laboratory equipment which has the capability to limit the equipment usage to authorized and certified users, locks and unlocks the equipment, and controls the real-time status of the equipment.","PeriodicalId":20443,"journal":{"name":"Proceedings","volume":"99 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136353492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Comprehensive Failure Analysis Approach Utilizing High-Resolution Targeted Patterns (HRTP) for ATPG Diagnosis Resolution Improvement, Test Coverage Resolution, and Further Fault Localization 利用高分辨率目标模式(HRTP)进行ATPG诊断分辨率改进、测试覆盖分辨率和进一步故障定位的综合故障分析方法
Proceedings Pub Date : 2023-11-12 DOI: 10.31399/asm.cp.istfa2023p0067
R. Estores, E. Barbian, L. Boukhanfra, K. Villareal, A. Sabate
{"title":"A Comprehensive Failure Analysis Approach Utilizing High-Resolution Targeted Patterns (HRTP) for ATPG Diagnosis Resolution Improvement, Test Coverage Resolution, and Further Fault Localization","authors":"R. Estores, E. Barbian, L. Boukhanfra, K. Villareal, A. Sabate","doi":"10.31399/asm.cp.istfa2023p0067","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2023p0067","url":null,"abstract":"Abstract This paper discusses a comprehensive failure analysis approach to digital failures. High-Resolution Targeted Patterns (HRTP) are highlighted along with their advantages in failure analysis by aiding in Automated Test Pattern Generation (ATPG) diagnoses resolution improvement, increasing the chance of detecting fault not detected by patterns implemented on Automated Test Equipment (ATE), determine a potential test screen, provide stimulus for further fault localization, and increase the analysis success rate. This comprehensive approach and the use of HRTP have proven very helpful in the analysis of internal requests and customer returns. Three cases will be discussed in this paper to highlight these advantages.","PeriodicalId":20443,"journal":{"name":"Proceedings","volume":"99 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136353499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Evaluation of Inductor for Solderability and Drop Damage Susceptibility 电感的可焊性和跌落损伤敏感性评估
Proceedings Pub Date : 2023-11-12 DOI: 10.31399/asm.cp.istfa2023p0034
Mack Marshall, Edward Huang, Arun Rajaraman, David Grosjean
{"title":"Evaluation of Inductor for Solderability and Drop Damage Susceptibility","authors":"Mack Marshall, Edward Huang, Arun Rajaraman, David Grosjean","doi":"10.31399/asm.cp.istfa2023p0034","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2023p0034","url":null,"abstract":"Abstract Lead-free solder joints tend to be more susceptible to brittle fracture, and thus susceptible to drop-damage. Drop testing of handheld ultrasound devices revealed broken solder joints on a large inductor component. Analysis of the cracks showed a dual intermetallic compound (IMC) layer of Ni3Sn4 (closest to the nickel) and (Ni,Cu)6Sn5, with the crack occurring in between the two layers. The inductor had a tinned nickel lead finish; the solder was SAC305 (a common lead-free solder comprising Sn, Ag, and Cu); and the printed circuit board (PCB) had a standard copper finish. The failure occurred very soon after manufacture and had not been enhanced by temperature cycling or aging, but it was not a time-zero failure: mechanical shocks from drops were required to propagate the crack through the joint fully. Strain measurements did not find any large strains after reflow and assembly, and no other components on the board showed cracking. There was no cracking observed at the PCB (Cu) side of the solder joint. The solution ultimately was to redesign the board, replacing the large single component with several smaller ones.","PeriodicalId":20443,"journal":{"name":"Proceedings","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136353501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Voltage Free Failure Analysis of Sub-15nm DRAM Gate Insulator Breakdown based on Thermal Laser Stimulation 基于热激光刺激的Sub-15nm DRAM栅极绝缘子击穿无电压失效分析
Proceedings Pub Date : 2023-11-12 DOI: 10.31399/asm.cp.istfa2023p0291
Chae Soo Kim, Bohyeon Jeon, Chiheon Byeon, Seungchul Yew, Dong In Lee, SeGuen Park, Hyodong Ban
{"title":"Voltage Free Failure Analysis of Sub-15nm DRAM Gate Insulator Breakdown based on Thermal Laser Stimulation","authors":"Chae Soo Kim, Bohyeon Jeon, Chiheon Byeon, Seungchul Yew, Dong In Lee, SeGuen Park, Hyodong Ban","doi":"10.31399/asm.cp.istfa2023p0291","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2023p0291","url":null,"abstract":"We propose an unbiased electrical fault isolation methodology for locating gate oxide breakdown failures in MOSFETs. The test vehicle involves a sub-15nm technology DRAM device which failed due to time-dependent dielectric breakdown (TDDB). This methodology introduces an implementation of Optical Beam Induced Resistance Change with no applied external bias (zero input voltage). From OBIRCH analysis, a change in current was achieved near failure site. This principle was explained based on Seebeck effect and equivalent circuit modeling of the MOSFET drain within Seebeck generator. A physical cross section using the Focused Ion Beam (FIB) revealed a gate oxide breakdown along the location of the OBIRCH spot, illustrating the benefit of an unbiased fault isolation to preserve the failure mechanism. This study proves that gate oxide breakdown site can still be located even with no external voltage applied, preserving the device condition of nanoscale DRAM, and eliminating the chances of altering the failure mechanism as a result of the applied external voltage stress.","PeriodicalId":20443,"journal":{"name":"Proceedings","volume":"100 18","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136352344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
In-Situ Global Ultra Thinning of Live Chip Backside for Digital Forensic and Failure Analysis 用于数字取证和失效分析的实时芯片背面原位超细化
Proceedings Pub Date : 2023-11-12 DOI: 10.31399/asm.cp.istfa2023p0205
Kees Schot, Aya Fukami
{"title":"In-Situ Global Ultra Thinning of Live Chip Backside for Digital Forensic and Failure Analysis","authors":"Kees Schot, Aya Fukami","doi":"10.31399/asm.cp.istfa2023p0205","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2023p0205","url":null,"abstract":"Abstract This paper presents an empirical investigation into the application of backside thinning techniques, while preserving the packaging integrity and mounting of the target system-on-a- chip (SoC) on a printed circuitboard (PCB) within a smartphone. Such thinning procedures are often indispensable in the domain of digital forensics, as they facilitate subsequent modifications to the SoC for in-depth analysis. Crucially, these modifications must be executed without compromising the core functionality of the target smartphone. By employing reactive ion etching, we effectively achieved comprehensive thinning of bulk side of a SoC with more than 100 mm2 surface area to a sub-10μm thickness.","PeriodicalId":20443,"journal":{"name":"Proceedings","volume":"100 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136352353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Inverter Characterization in Advanced Process by Nanoprobing 先进工艺中逆变器的纳米探针表征
Proceedings Pub Date : 2023-11-12 DOI: 10.31399/asm.cp.istfa2023p0246
J.S. Tsai, C.H. Yen, D.Y. Tzou, K.T. Ho
{"title":"Inverter Characterization in Advanced Process by Nanoprobing","authors":"J.S. Tsai, C.H. Yen, D.Y. Tzou, K.T. Ho","doi":"10.31399/asm.cp.istfa2023p0246","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2023p0246","url":null,"abstract":"Abstract As the semiconductor process node enters into advanced process era, it is more challenging to extract electrical behavior of devices and circuits by nanoprobing systems. Not only probing is getting difficult at smaller contact or via, but also the deprocess tricks would have large influence on probing conditions, which could cause incorrect electrical performance and hard to explain the reasons. This research develops the technique of sample preparation to extract correct transfer curve of inverter cell in FinFET process.","PeriodicalId":20443,"journal":{"name":"Proceedings","volume":"100 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136352355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Reliable Backside IC Preparation Down to STI Level Using Chemical Mechanical Polishing (CMP) with Highly Selective Slurry 使用高选择性浆料的化学机械抛光(CMP)，可靠的背面IC制备达到STI水平
Proceedings Pub Date : 2023-11-12 DOI: 10.31399/asm.cp.istfa2023p0265
Norbert Herfurth, Awwal A. Adesunkanmi, Gerfried Zwicker, Christian Boit
{"title":"Reliable Backside IC Preparation Down to STI Level Using Chemical Mechanical Polishing (CMP) with Highly Selective Slurry","authors":"Norbert Herfurth, Awwal A. Adesunkanmi, Gerfried Zwicker, Christian Boit","doi":"10.31399/asm.cp.istfa2023p0265","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2023p0265","url":null,"abstract":"Abstract When aiming for extreme thinning of the bulk silicon down to the shallow trench isolation (STI) level, endpoint determination is a challenging task. Here, we present a novel approach providing reliable access to the STI level of single dies. Therefore, we transfer the wafer-based CMP process to be applicable to single dies on a table-top machine. In a first step, the developed process is applied to the whole IC backside simultaneously. Using a highly selective slurry with a material removal ratio from Si to SiO of more than 500:1 ensures that the STI level remains intact. Two types of samples have been prepared for experiments performed for this paper. A 115mm x 80mm flip-chip bonded device with a bulk silicon thickness of 500μm has been prepared to STI level within less than 4 hours.","PeriodicalId":20443,"journal":{"name":"Proceedings","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136352361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The Sulfide Contamination Management in Circuit Probing FAB Clean Room Environment 电路探测FAB洁净室环境中的硫化物污染管理
Proceedings Pub Date : 2023-11-12 DOI: 10.31399/asm.cp.istfa2023p0209
Kuan-Jui Tu, Frank Su, Wen-Fei Hsieh, Vincent Chen, Henry Lin, Y.S. Lou
{"title":"The Sulfide Contamination Management in Circuit Probing FAB Clean Room Environment","authors":"Kuan-Jui Tu, Frank Su, Wen-Fei Hsieh, Vincent Chen, Henry Lin, Y.S. Lou","doi":"10.31399/asm.cp.istfa2023p0209","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2023p0209","url":null,"abstract":"Abstract Sulfur corrodes silver metal in a continuous reaction. This corrosion is also found in semiconductor industry processes for the application of silver into Backside Grinding & Backside Metal (BGBM). In this paper two experiments were conducted for the sulfide corrosion behavior in a Circuit Probing (CP) clean room environment. They were Mixed Flowing Gas (MFG) and clean room environment exposure test. The MFG test of this research was conducted in a testing chamber with temperature, relative humidity, and concentration of H2S were carefully controlled and monitored. The MFG test conditions included the test temperature of 25°C, relative humidity of 75 %, and H2S gas concentration of 10 ppb. And the MFG tests lasted for over 72 hours. The X-ray photoelectron spectroscopy (XPS) was used to analyze the elements composition and Ag2S film thickness of the MFG test samples. The second test of this research was the direct exposure experiment. The silicon samples deposited with appropriate silver layer thickness were exposed in CP fab clean room environment with H2S concentration well monitored. The XPS analysis results of the corresponding exposure test samples indicated that the Ag2S contamination would continue to develop and wouldn't saturate. This would be indicative for the management of Ag2S contamination control. The results of MFG and Exposure test were help for Ardentec to setup Ag2S corrosion methodology. All the managements were applied into daily operation of the BGBM semiconductor products.","PeriodicalId":20443,"journal":{"name":"Proceedings","volume":"99 26","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136352362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Non-Destructive Defect Localization by Scanning Acoustic Microscopy 扫描声学显微镜无损缺陷定位
Proceedings Pub Date : 2023-11-12 DOI: 10.31399/asm.cp.istfa2023tpy1
Sebastian Brand, Michael Kögel
{"title":"Non-Destructive Defect Localization by Scanning Acoustic Microscopy","authors":"Sebastian Brand, Michael Kögel","doi":"10.31399/asm.cp.istfa2023tpy1","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2023tpy1","url":null,"abstract":"Abstract Presentation slides for the ISTFA 2023 Tutorial session “Non-Destructive Defect Localization by Scanning Acoustic Microscopy.”","PeriodicalId":20443,"journal":{"name":"Proceedings","volume":"101 19","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136352524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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