Proceedings最新文献_第8页

Spatial Resolution Enhancement of Time-Resolved Photon Emission Imaging with Superconducting Nanowire Single Photon Detector 利用超导纳米线单光子探测器增强时间分辨光子发射成像的空间分辨率

Proceedings Pub Date : 2023-11-12 DOI: 10.31399/asm.cp.istfa2023p0220

Norimichi Chinone, Hirotoshi Terada, Tomonori Nakamura, Yoshiyuki Yokoyama, Toru Matsumoto

引用次数: 0

Electron Beam Induced Resistance Change for Isolation of Wordline Shorts in 3D Replacement Gate NAND 电子束诱导的三维替换栅NAND中字线短路隔离的电阻变化

Proceedings Pub Date : 2023-11-12 DOI: 10.31399/asm.cp.istfa2023p0197

Chandler Rich, Wayne Harlow, Becky Muñoz, Regino Sandoval, J. Temo Davis, Scott Williams

引用次数: 0

Methods to Enhance Infrared Imaging for Defect Localization Using Lock-in Thermography 利用锁定热成像增强红外成像缺陷定位的方法

Proceedings Pub Date : 2023-11-12 DOI: 10.31399/asm.cp.istfa2023p0155

Anjanashree M.R. Sharma, Kristof J.P. Jacobs, Ingrid De Wolf

{"title":"Methods to Enhance Infrared Imaging for Defect Localization Using Lock-in Thermography","authors":"Anjanashree M.R. Sharma, Kristof J.P. Jacobs, Ingrid De Wolf","doi":"10.31399/asm.cp.istfa2023p0155","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2023p0155","url":null,"abstract":"Abstract In this paper, we demonstrate three approaches to enhance the topographical contrast of infrared images obtained from lockin thermography (LIT). Infrared imaging, particularly LIT, is one of the extensively used techniques for failure analysis (FA) in the semiconductor industry. However, low-contrast topography images are obtained at room temperature from conventional LIT due to poor emissivity contrast in the devices and the limitation on the performance of the infrared camera. The gray-scale topographical contrast is improved by 85% when the device under test is heated from room temperature to 75°C, using a printed circuit board heater. Furthermore, a heat-assisted LIT approach is proposed and demonstrated at the die level on an electrically leaky silicon interposer sample. The topographical contrast and the signal intensity of the hotspot obtained are enhanced when compared to the classical LIT, which is performed at room temperature. Further, the dual LIT approach is developed to reduce the thermal budget of the heat-assisted approach. The hotspot amplitude and improved topography image are obtained from two consecutive lock-in measurements. In addition, the topography image from this technique is obtained by averaging several hundred frames from the camera for a period of ten minutes, which results in an image that is less susceptible to input noise levels. To increase the throughput of the FA process, quadrature lock-in thermography, a dual-purpose measurement technique is shown. A high-contrast topography image and the hotspot location are obtained from the same lock-in thermogram by performing trigonometric conditioning. The throughput from this approach is the same as the classical LIT technique.","PeriodicalId":20443,"journal":{"name":"Proceedings","volume":"99 22","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136352366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Machine Learning Based Data and Signal Analysis Methods for the Application in Failure Analysis (2023 Update) 基于机器学习的数据和信号分析方法在故障分析中的应用(2023更新)

Proceedings Pub Date : 2023-11-12 DOI: 10.31399/asm.cp.istfa2023tpw1

Michael Kögel, Sebastian Brand, Frank Altmann

引用次数: 0

ESD Challenges in Advanced CMOS Technologies—Designing Diode Based ESD Protection 先进CMOS技术中的ESD挑战——设计基于二极管的ESD保护

Proceedings Pub Date : 2023-11-12 DOI: 10.31399/asm.cp.istfa2023tpa1

Shih-Hung Chen

引用次数: 0

An Artificial Intelligence Powered Resolution Recovery Technique and Workflow to Accelerate Package Level Failure Analysis with 3D X-ray Microscopy 人工智能驱动的分辨率恢复技术和工作流程，以加速封装级故障分析与3D x射线显微镜

Proceedings Pub Date : 2023-11-12 DOI: 10.31399/asm.cp.istfa2023p0443

Syahirah Mohammad-Zulkifli, Bernice Zee, Qiu Wen, Maverique Ong, Yanjing Yang, Andriy Andreyev, Masako Terada, Allen Gu

{"title":"An Artificial Intelligence Powered Resolution Recovery Technique and Workflow to Accelerate Package Level Failure Analysis with 3D X-ray Microscopy","authors":"Syahirah Mohammad-Zulkifli, Bernice Zee, Qiu Wen, Maverique Ong, Yanjing Yang, Andriy Andreyev, Masako Terada, Allen Gu","doi":"10.31399/asm.cp.istfa2023p0443","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2023p0443","url":null,"abstract":"Abstract 3D X-ray microscopy (XRM) is an effective highresolution and non-destructive tool for semiconductor package level failure analysis. One limitation with XRM is the ability to achieve high-resolution 3D images over large fields of view (FOVs) within acceptable scan times. As modern semiconductor packages become more complex, there are increasing demands for 3D X-ray instruments to image encapsulated structures and failures with high productivity and efficiency. With the challenge to precisely localize fault regions, it may require high-resolution imaging with a FOV of tens of millimeters. This may take over hundreds of hours of scans if many high-resolution but small-volume scans are performed and followed with the conventional 3D registration and stitches. In this work, a novel deep learning reconstruction method and workflow to address the issue of achieving highresolution imaging over a large FOV is reported. The AI powered technique and workflow can be used to restore the resolution over the large FOV scan with only a high-resolution and a large FOV scan. Additionally, the 3D registration and stitch workflow are automated to achieve the large FOV images with a recovered resolution comparable to the actual high-resolution scan.","PeriodicalId":20443,"journal":{"name":"Proceedings","volume":"97 21","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136353177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Precise Final Thinning by Concentrated Ar Ion Beam Milling of Plan View TEM Specimens from Phase Change Memory Device Prepared in Xe Plasma FIB 用浓氩离子束铣削Xe等离子体FIB制备相变存储器件平面透射电镜样品的精确最终减薄

Proceedings Pub Date : 2023-11-12 DOI: 10.31399/asm.cp.istfa2023p0309

C.S. Bonifacio, M.L. Ray, P.E. Fischione, Y. Yu, M. Skowronski

引用次数: 0

Advances in EFA with Color Coded Multi-Channel Nanoprobing 彩色编码多通道纳米探针EFA研究进展

Proceedings Pub Date : 2023-11-12 DOI: 10.31399/asm.cp.istfa2023p0427

Grigore Moldovan, William Courbat, Jörg Jatzkowski

引用次数: 0

Avalon-Aided Mapping of Fault-Localized Area of ADI’s RADAR Receive Path Analog Front-End (AFE) Amplifier with 0.18um 6-Metal CMOS Fab Process 基于0.18um 6金属CMOS工艺的ADI公司雷达接收路径模拟前端(AFE)放大器故障局部区域的阿瓦隆辅助映射

Proceedings Pub Date : 2023-11-12 DOI: 10.31399/asm.cp.istfa2023p0078

Arnulfo Evangelista, Janella Alfelor-Igtiben, John David Mangali, Khristopherson Cajucom

{"title":"Avalon-Aided Mapping of Fault-Localized Area of ADI’s RADAR Receive Path Analog Front-End (AFE) Amplifier with 0.18um 6-Metal CMOS Fab Process","authors":"Arnulfo Evangelista, Janella Alfelor-Igtiben, John David Mangali, Khristopherson Cajucom","doi":"10.31399/asm.cp.istfa2023p0078","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2023p0078","url":null,"abstract":"Abstract Analog Devices Inc. (ADI)’s Radar Receive Path Analog Front End Amplifier (AFE) with a 0.18um 6-metal Fab Process has failures related to Power-Down and Scan test parameters which were endorsed for Failure Analysis. Fault localization is quite challenging because it involves 6 metal layers. This has been resolved with the availability of Synopsis Avalon software with capability to convert the complete Cadence schematics and layout that is usable for Failure Analysis, through cross-mapping with the fault localized area-of-interest (AOI) on the actual reject part with the die schematics and layout, and identifying the failing component and circuit block. This leads to the creation of the failure model related to the reported failure mode and the determination of the appropriate failure mechanism related to fabrication defects between the adjacent metallization layers and defects on between the polysilicon and substrate layer. This helps speed up the FA Cycle Time and achieve an accurate failure mechanism, which later resolves the fab defect issue with the Fab process owner.","PeriodicalId":20443,"journal":{"name":"Proceedings","volume":"98 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136353343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Electrons Vs. Photons: Assessment of Circuit’s Activity Requirements for E-Beam and Optical Probing Attacks 电子与光子:电子束和光学探测攻击的电路活动性要求评估

Proceedings Pub Date : 2023-11-12 DOI: 10.31399/asm.cp.istfa2023p0339

Elham Amini, Tuba Kiyan, Lars Renkes, Thilo Krachenfels, Christian Boit, Jean-Pierre Seifert, Jörg Jatzkowski, Frank Altmann, Sebastian Brand, Shahin Tajik

引用次数: 0