{"title":"用于数字取证和失效分析的实时芯片背面原位超细化","authors":"Kees Schot, Aya Fukami","doi":"10.31399/asm.cp.istfa2023p0205","DOIUrl":null,"url":null,"abstract":"Abstract This paper presents an empirical investigation into the application of backside thinning techniques, while preserving the packaging integrity and mounting of the target system-on-a- chip (SoC) on a printed circuitboard (PCB) within a smartphone. Such thinning procedures are often indispensable in the domain of digital forensics, as they facilitate subsequent modifications to the SoC for in-depth analysis. Crucially, these modifications must be executed without compromising the core functionality of the target smartphone. By employing reactive ion etching, we effectively achieved comprehensive thinning of bulk side of a SoC with more than 100 mm2 surface area to a sub-10μm thickness.","PeriodicalId":20443,"journal":{"name":"Proceedings","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2023-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"In-Situ Global Ultra Thinning of Live Chip Backside for Digital Forensic and Failure Analysis\",\"authors\":\"Kees Schot, Aya Fukami\",\"doi\":\"10.31399/asm.cp.istfa2023p0205\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Abstract This paper presents an empirical investigation into the application of backside thinning techniques, while preserving the packaging integrity and mounting of the target system-on-a- chip (SoC) on a printed circuitboard (PCB) within a smartphone. Such thinning procedures are often indispensable in the domain of digital forensics, as they facilitate subsequent modifications to the SoC for in-depth analysis. Crucially, these modifications must be executed without compromising the core functionality of the target smartphone. By employing reactive ion etching, we effectively achieved comprehensive thinning of bulk side of a SoC with more than 100 mm2 surface area to a sub-10μm thickness.\",\"PeriodicalId\":20443,\"journal\":{\"name\":\"Proceedings\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2023-11-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.31399/asm.cp.istfa2023p0205\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.31399/asm.cp.istfa2023p0205","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In-Situ Global Ultra Thinning of Live Chip Backside for Digital Forensic and Failure Analysis
Abstract This paper presents an empirical investigation into the application of backside thinning techniques, while preserving the packaging integrity and mounting of the target system-on-a- chip (SoC) on a printed circuitboard (PCB) within a smartphone. Such thinning procedures are often indispensable in the domain of digital forensics, as they facilitate subsequent modifications to the SoC for in-depth analysis. Crucially, these modifications must be executed without compromising the core functionality of the target smartphone. By employing reactive ion etching, we effectively achieved comprehensive thinning of bulk side of a SoC with more than 100 mm2 surface area to a sub-10μm thickness.