Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)最新文献_第5页

Oscillation Built-In-Self-Test for ADC linearity testing in deep submicron CMOS technology 深亚微米CMOS技术中ADC线性度测试的振荡内置自检

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-10-24 DOI: 10.1109/ASQED.2013.6643589

Koay Soon Chan, Nuzrul Fahmi Nordin, Kim Chon Chan, Terk Zyou Lok, C. W. Yong, A. Osseiran

引用次数: 1

An efficient metric for detecting timing failure region due to crosstalk noise 一种检测串扰噪声引起的时序失效区域的有效度量

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-10-24 DOI: 10.1109/ASQED.2013.6643607

Hyoeon Yang, Young Hwan Kim

引用次数: 0

A low-power circuit architecture for transistor electrical overstress (EOS) protection 一种晶体管电过压(EOS)保护的低功耗电路结构

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-10-24 DOI: 10.1109/ASQED.2013.6643601

Aw Chee Hong

{"title":"A low-power circuit architecture for transistor electrical overstress (EOS) protection","authors":"Aw Chee Hong","doi":"10.1109/ASQED.2013.6643601","DOIUrl":"https://doi.org/10.1109/ASQED.2013.6643601","url":null,"abstract":"As the transistor dimension keeps shrinking following trend predicted by Moore's Law, the voltage that transistor can sustain reliably is also reducing. For certain serial interface protocols (like the ubiquitous Universal Serial Bus (USB)) and some legacy input/output interfaces, high voltages like 1.8V, 3.3V and even 5.0V are still being used for protocol compliance. It is costly in silicon fabrication to provide transistors with different gate-oxide thickness to cater for various high voltage and speed requirements. In order to minimize the type of gate oxide thickness in advanced silicon process, circuit innovation is usually required to enable transistor to operate with voltage higher than its reliability limit, yet protected from electrical overstress (EOS). This paper discusses a new circuit architecture that is able to detect voltage source as well as to switch between external source and internal biasing voltage to ensure all transistors operating with high voltage are not exposed to the voltage limit. This circuit is low power in nature since it does not consume static current. By having this protection scheme, this would enable the use of transistor to support high-voltage application without incurring cost of having additional thicker gate-oxide transistor. In terms of application, this architecture can be used in integrated chip design involving various high-voltage supplies.","PeriodicalId":198881,"journal":{"name":"Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131668752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Tunable stochastic computing using layered synthesis and temperature adaptive voltage scaling 基于分层合成和温度自适应电压标度的可调随机计算

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-10-24 DOI: 10.1109/ASQED.2013.6643572

Neel Gala, V. Devanathan, V. Visvanathan, Virat Gandhi, V. Kamakoti

引用次数: 2

Implementation of a physical unclonable function (PUF) with transmission line crosstalk in a chip 在芯片中实现具有传输线串扰的物理不可克隆功能

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-10-24 DOI: 10.1109/ASQED.2013.6643594

Kyoungrok Cho, Kwan-hee Lee, Seung-Yul Kim, Sang-Jin Lee, Younggap You

{"title":"Implementation of a physical unclonable function (PUF) with transmission line crosstalk in a chip","authors":"Kyoungrok Cho, Kwan-hee Lee, Seung-Yul Kim, Sang-Jin Lee, Younggap You","doi":"10.1109/ASQED.2013.6643594","DOIUrl":"https://doi.org/10.1109/ASQED.2013.6643594","url":null,"abstract":"A physically unclonable function (PUF) is a promising technology that provides the ability to identify network components. Conventional PUF circuitry suffers from a reliability problem in which a consistent output value is not guaranteed because of environmental changes such as the power supply voltage and operating temperature. This paper introduces a PUF circuit that yields consistent responses that overcome fluctuations in the operating conditions. The proposed PUF is based on the variation in the crosstalk between adjacent transmission lines, which reflects the random physical structure of interconnected lines. The proposed PUF cell comprises three transmission lines and a sense amplifier. The sense amplifier catches the crosstalk differences between two adjacent transmission lines. The crosstalk differences reflect a physical structure variation, which is immune to changes in the operating environment. The proposed PUF circuit yields a well-balanced distribution probability, (100/2n)%, for each challenge bit with σ = 1%. The identification generated by the PUF can be regarded as core functionality for authentication and encryption in security applications.","PeriodicalId":198881,"journal":{"name":"Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)","volume":"263 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123100786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A coverage driven test generation methodology using consistency algorithm 使用一致性算法的覆盖驱动测试生成方法

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-10-24 DOI: 10.1109/ASQED.2013.6643559

M. P. J. George, O. Mohamed

引用次数: 1

Innovative solutions for Package on Package test 创新的包装测试解决方案

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-10-24 DOI: 10.1109/ASQED.2013.6643580

Chin Chien Tee, Siang Soh

引用次数: 0

On using IEEE 1500 standard for functional testing 关于使用IEEE 1500标准进行功能测试

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-10-24 DOI: 10.1109/ASQED.2013.6643561

Ghazanfar Ali, F. Hussin, N. Ali, N. H. Hamid

引用次数: 1

Heat transfer in high-power LED with thermally conductive particle-filled epoxy composite as thermal interface material for system-level analysis 以导热颗粒填充环氧复合材料为热界面材料的大功率LED传热系统级分析

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-08-01 DOI: 10.1109/ASQED.2013.6643610

P. Anithambigai, S. Shanmugan, D. Mutharasu, K. Ibrahim

引用次数: 4

Logic emulation with forced assertions: A methodology for rapid functional verification and debug 带有强制断言的逻辑仿真:一种用于快速功能验证和调试的方法

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-08-01 DOI: 10.1109/ASQED.2013.6643605

Somnath Banerjee, T. Gupta, Sanjay Gupta

{"title":"Logic emulation with forced assertions: A methodology for rapid functional verification and debug","authors":"Somnath Banerjee, T. Gupta, Sanjay Gupta","doi":"10.1109/ASQED.2013.6643605","DOIUrl":"https://doi.org/10.1109/ASQED.2013.6643605","url":null,"abstract":"To improve debugging turnaround time of complex System-on-chip (SoC) designs on FPGA based logic emulation systems, it is important to minimize the iterations through design recompilation or FPGA reconfiguration process for validating repeated debugging changes. This paper presents a methodology for modeling debugging changes in terms of standalone assertion statements and evaluating their effect by running emulation without requiring any design modification or recompilation step, during emulation based debug. The set of assertions representing debugging changes are transformed into a set of constraints that are directly programmed into the emulator and an associated logic analyzer. When emulation is resumed from a bug-free state, these constraints are enforced by automatically forcing necessary signals to desired values, according to the specified assertions. Multiple debugging changes can thus be verified before eventually porting the fixes to design RTL followed by recompilation and emulation rerun. The proposed methodology also facilitates block based SoC development, by allowing a designer to enforce the correct functional behavior of some other block whose output affects the behavior of the block he is working on. Application of the proposed debugging system to debugging of real industry standard designs has been seen to reduce debugging turn-around time significantly.","PeriodicalId":198881,"journal":{"name":"Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124871152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3