Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)最新文献_第6页

On improving at no cost the quality of products built with SRAM-based FPGAs 关于用基于sram的fpga免费提高产品质量

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-08-01 DOI: 10.1109/ASQED.2013.6643603

R. Leveugle, Mohamed Ben Jrad

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引用次数: 2

Optimization of thermal vias for thermal resistance in FR-4 PCBs FR-4 pcb热阻热通孔的优化

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-08-01 DOI: 10.1109/ASQED.2013.6643611

Alex Lee Yuen Beng, Gan Sik Hong, M. Devarajan

引用次数: 3

Variability aware performance evaluation of low power SRAM cell 低功耗SRAM单元可变性感知性能评估

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-08-01 DOI: 10.1109/ASQED.2013.6643584

H. Dsilva, J. Pinto, Arzan Elchidana, S. Mande

引用次数: 2

Study on silicon window polarity of partial-SOI LDMOS power devices 部分soi LDMOS功率器件硅窗极性研究

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-08-01 DOI: 10.1109/ASQED.2013.6643600

Yue Hu, Hao Wang, Cheng Wang, Jin He, Xiaoan Zhu, Sheng Chang, Qijun Huang, D. Wang, Qingxing He, Caixia Du, Shengju Zhong

引用次数: 1

Path resistance reduction through automated Multi-Level Metal and Via insertion for IC layout design 通过自动多级金属和通孔插入来降低路径电阻，用于IC布局设计

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-08-01 DOI: 10.1109/ASQED.2013.6643597

Thai Lee Lo, Gregory Sylvester Emmanuel, Thomas Fong Chee Goh, Chun Keong Lee, Joon Heong Ong, Yng Chuk Tam, Jonathan Yoong Seang Ong, Hui Peng Ong

{"title":"Path resistance reduction through automated Multi-Level Metal and Via insertion for IC layout design","authors":"Thai Lee Lo, Gregory Sylvester Emmanuel, Thomas Fong Chee Goh, Chun Keong Lee, Joon Heong Ong, Yng Chuk Tam, Jonathan Yoong Seang Ong, Hui Peng Ong","doi":"10.1109/ASQED.2013.6643597","DOIUrl":"https://doi.org/10.1109/ASQED.2013.6643597","url":null,"abstract":"Current EDA market has plenty of DFM (Design for Manufacturing) solutions on via doubling for VLSI design which enhances single-level metal (hierarchy) interconnections. A new conceptual approach, Multi-Level Metal and Via (MLMV) is proposed to extend the capability to insert metals and vias across multiple hierarchies to lower effective resistance. The objective is to improve signal integrity by reducing resistance across metal paths for individual signals, inclusive of supplies across the full chip. MLMV also takes into consideration the critical signals integrity of the design. The tool ensures no metal insertion is too close to critical signals, to prevent potential noise in the design. The results discussed in this paper show a significant improvement in terms of reducing the effective resistance of experimental test case signal path up to 90% in comparing to the conventional via filling solution. With these significant results, it can be concluded that MLMV is able to populate the metal and via effectively and minimizing resistance in the design.","PeriodicalId":198881,"journal":{"name":"Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129889431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Influence of phosphor packaging configurations on the optical performance of Chip on Board phosphor converted Warm White LEDs 荧光粉封装结构对片上荧光粉转换暖白光led光学性能的影响

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-08-01 DOI: 10.1109/ASQED.2013.6643608

P. H. Yuen, Hwang Hsien Shiung, M. Devarajan

引用次数: 5

Simultaneous hotspot temperature and supply noise reductions using thermal TSVs and decoupling capacitors 使用热tsv和去耦电容器同时降低热点温度和电源噪声

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2011-08-29 DOI: 10.1109/ASQED.2013.6643595

Yan-Wun Wang, Pao-Jen Huang, Tai-Chen Chen, C. Liu

引用次数: 0