Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)最新文献

Full system power delivery analysis for single ended interface 单端接口全系统功率输出分析

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-10-24 DOI: 10.1109/ASQED.2013.6643577

H. Shu, B. E. Cheah, J. Kong, S. G. Pang, Li Chuang Quek

引用次数: 1

Cluster-based thermal-aware 3D-floorplanning technique with post-floorplan TTSV insertion at via-channels 基于集群的热感知3d地板规划技术，通过通道插入TTSV

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-10-24 DOI: 10.1109/ASQED.2013.6643588

Chia-chen Wen, Ying-Jung Chen, S. Ruan

引用次数: 3

A new TSV set architecture for high reliability 一种新的TSV集架构，具有高可靠性

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-10-24 DOI: 10.1109/ASQED.2013.6643574

Jaeseok Park, Sungho Kang

引用次数: 1

A possibility of crystalline Indium-Gallium-Zinc-Oxide 铟镓锌氧化物结晶的可能性

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-10-24 DOI: 10.1109/ASQED.2013.6643553

S. Yamazaki

引用次数: 8

The effects of elliptical gate cross section on carbon nanotube gate-all-around field effect transistor 椭圆栅极截面对碳纳米管栅极-全能场效应晶体管的影响

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-10-24 DOI: 10.1109/ASQED.2013.6643599

Hao Wang, Sheng Chang, Cheng Wang, Yue Hu, Hongyu He, Jin He, Qingxing He, Caixia Du, Shengju Zhong

引用次数: 2

Heterogeneous stacking of 3D MPSoC architecture: Physical implementation analysis and performance evaluation 三维MPSoC架构的异构堆叠:物理实现分析和性能评估

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-10-24 DOI: 10.1109/ASQED.2013.6643575

M. H. Jabbar, D. Houzet, O. Hammami

{"title":"Heterogeneous stacking of 3D MPSoC architecture: Physical implementation analysis and performance evaluation","authors":"M. H. Jabbar, D. Houzet, O. Hammami","doi":"10.1109/ASQED.2013.6643575","DOIUrl":"https://doi.org/10.1109/ASQED.2013.6643575","url":null,"abstract":"3D integration is one of the feasible technologies for producing advanced computing architecture to support ever-increasing demand of higher performance computing especially in mobile devices. The emerging trend of multiprocessor architecture has made Network on Chip (NoC) architecture the best solution for future manycore architecture devices. In this work, we explore the implementation of heterogeneous 3D Multiprocessor System on Chip (MPSoC) stacking architecture and evaluate its performance in terms of timing and power consumption compared with its 2D counterpart. The proposed heterogeneous 3D MPSoC implementation approach is considered to be the best solution for the time being as there are no 3D-aware EDA tools available in the markets that capable of performing 3D optimization as in 2D EDA tools. We also perform physical implementation analysis on the clock tree structure between 2D and 3D architecture and examine the impact of using 2D EDA tools for designing 3D architecture. The implementation is based on industry-specific Tezzaron 3D IC technology and the evaluation is based on the GDSII results from physical design implementations.","PeriodicalId":198881,"journal":{"name":"Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130507831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Improved test methodology for multi-clock domain SoC ATPG testing 改进的测试方法多时钟域SoC ATPG测试

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-10-24 DOI: 10.1109/ASQED.2013.6643560

Ee Mei Ooi, Chin Hai Ang

引用次数: 1

Exploration of 2D EDA tool impact on the 3D MPSoC architectures performance 探索2D EDA工具对3D MPSoC架构性能的影响

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-10-24 DOI: 10.1109/ASQED.2013.6643596

M. H. Jabbar, A. M'zah, O. Hammami, D. Houzet

{"title":"Exploration of 2D EDA tool impact on the 3D MPSoC architectures performance","authors":"M. H. Jabbar, A. M'zah, O. Hammami, D. Houzet","doi":"10.1109/ASQED.2013.6643596","DOIUrl":"https://doi.org/10.1109/ASQED.2013.6643596","url":null,"abstract":"The need for higher performance devices to enable more complex applications continues to drive the growth of electronic design especially in the mobile markets. 3D integration is one of the feasible technologies to increase the system's performance and device integration by stacking multiple dies interconnected using through silicon vias (TSV). NoC-based Multiprocessor System on Chip (MPSoC) architecture has become the primary technology to provide higher performance to support more complex applications. In this paper, we perform an exploration and analysis of 2D EDA tool parameters impact on the 3D MPSoC architectures (3D Mesh MPSoC and heterogeneous 3D MPSoC stacking) performance in terms of timing and power characteristics. Exploration results show that the 2D EDA tool parameters have strong impact on the timing performance compared with power consumption. Furthermore, it is also shown that heterogeneous 3D MPSoC architecture has less footprint area, higher speed and less power consumption compared with 3D Mesh MPSoC for the same number of processing elements suggesting that it is a better design approach considering the limitation capability of 2D EDA tools for 3D design.","PeriodicalId":198881,"journal":{"name":"Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116203525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A fast transient response synchronous Buck converter with modified ripple-based control (MRBC) technique 基于改进纹波控制(MRBC)技术的快速瞬态响应同步降压变换器

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-10-24 DOI: 10.1109/ASQED.2013.6643556

Yunwu Zhang, Jing Zhu, Weifeng Sun, Y. Yi

引用次数: 1

Ultra-sensitive polymeric sensor platforms for environmental sensing applications 用于环境传感应用的超灵敏聚合物传感器平台

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-10-24 DOI: 10.1109/ASQED.2013.6643562

P. Ray, H. N. Raval, V. Rao

引用次数: 0