Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)最新文献_第2页

Totally self-checking (TSC) VLSI circuits using Scalable Error Detection Coding (SEDC) technique 采用可扩展错误检测编码(SEDC)技术的完全自检(TSC) VLSI电路

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-10-24 DOI: 10.1109/ASQED.2013.6643567

Natarajan Somasundaram, Farhad Mehdipour, Jeong-A Lee, N. Ramadass, Y. V. R. Rao

{"title":"Totally self-checking (TSC) VLSI circuits using Scalable Error Detection Coding (SEDC) technique","authors":"Natarajan Somasundaram, Farhad Mehdipour, Jeong-A Lee, N. Ramadass, Y. V. R. Rao","doi":"10.1109/ASQED.2013.6643567","DOIUrl":"https://doi.org/10.1109/ASQED.2013.6643567","url":null,"abstract":"Integrated circuits fabricated in deep sub-micron technology are vulnerable to intermittent or transient faults which are the predominant cause of system failures. With continued scaling, operating voltage levels have reduced and resultant decrease in noise margins, the possibility of transient faults is likely to increase. Also, during operation in adverse environments, transient faults occur upon exposure to ionizing radiations and neutron effects. These faults manifest themselves as unidirectional errors. The ability to operate in the intended manner even in the presence of faults is an important objective of all electronic systems. Totally Self-checking (TSC) circuits permit online detection of hardware faults. The Scalable Error Detection Coding (SEDC) technique used to design self-checking circuits with faster execution and lesser latency overhead for use in fault-tolerant VLSI circuits is presented. SEDC technique is formulated and architecture is designed in such a way that for any input binary data length, only area is scaled, with a constant latency of two logic gates and requires only a single clock cycle for generating SEDC code. It is shown that the proposed SEDC technique is found to be significantly efficient than the existing unidirectional error detection techniques in terms of speed, latency, area and achieving 100% error detection.","PeriodicalId":198881,"journal":{"name":"Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126337552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Optimized clock gating cell for low power design in nanoscale CMOS technology 基于纳米级CMOS技术的低功耗设计优化时钟门控单元

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-10-24 DOI: 10.1109/ASQED.2013.6643569

Aniryudh Reddy Durgam, K. Choi

引用次数: 4

Distortion analysis and calculation of wide-band track and hold amplifier 宽带轨道保持放大器失真分析与计算

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-10-24 DOI: 10.1109/ASQED.2013.6643585

Hailang Liang, Jin He, Cheng Wang, R. Evans, E. Skafidas, Qingxing He, Caixia Du, Shengju Zhong

引用次数: 0

On testing of MEDA based digital microfluidics biochips 基于MEDA的数字微流控生物芯片的测试

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-10-24 DOI: 10.1109/ASQED.2013.6643565

V. Shukla, N. Ali, F. Hussin, Mark Zwolinski

引用次数: 17

Computationally efficient methodology for statistical characterization and yield estimation due to inter- and intra-die process variations 计算有效的方法，统计特性和良率估计由于模具间和内部工艺变化

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-10-24 DOI: 10.1109/ASQED.2013.6643602

S. Mande, A. Chandorkar, H. Iwai

{"title":"Computationally efficient methodology for statistical characterization and yield estimation due to inter- and intra-die process variations","authors":"S. Mande, A. Chandorkar, H. Iwai","doi":"10.1109/ASQED.2013.6643602","DOIUrl":"https://doi.org/10.1109/ASQED.2013.6643602","url":null,"abstract":"In this paper, first we have demonstrated the suitability of Plackett-Burman Design of Experiment (PB-DOE) method for the sensitivity analysis of a device and a circuit performance to inter- and intra-die process variations. Further, it is shown that PB-DOE method takes relatively less computational time and provides reasonable accuracy as compared to standard Monte Carlo Method. In the next part of the work, computationally efficient methodology for timing yield analysis of standard CMOS cells is proposed. The proposed technique combines well-known statistical methods namely Principal Component Analysis (PCA) and PB-DOE method. Here, the proposed technique is successfully implemented for timing yield estimation of standard CMOS cell implemented in non-planar Double-Gate (DG) FinFET technology. However, our methodology is independent of technology platform and can be implemented on classical bulk CMOS technology or any other emerging technologies too. Furthermore, it is shown that the proposed methodology reduces the computational cost by 35% as compared RSM based Monte Carlo method.","PeriodicalId":198881,"journal":{"name":"Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131758960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Thermal simulation analysis of high power LED system using two-resistor compact LED model 采用双电阻紧凑型LED模型的大功率LED系统热仿真分析

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-10-24 DOI: 10.1109/ASQED.2013.6643609

Z. Ong, S. Subramani, M. Devarajan

{"title":"Thermal simulation analysis of high power LED system using two-resistor compact LED model","authors":"Z. Ong, S. Subramani, M. Devarajan","doi":"10.1109/ASQED.2013.6643609","DOIUrl":"https://doi.org/10.1109/ASQED.2013.6643609","url":null,"abstract":"This paper presents the thermal analysis and validation of high power LED system with simulation and experimental methods. A 3W high power LED package is mounted on MCPCB and heat sink, which is tested inside a (300 × 300 × 300mm) still air chamber with three different forward currents. Experimental measurement with Thermal Transient Tester (T3Ster) is performed to capture the thermal transient characteristic of the LED system. The simulation is conducted with FloEFD 12.1 CFD software, using two-resistor model the LED package is defined with thermal resistance at different forward current. From the validation the simulation result closely match the experimental result, with highest percentage error at 4.75%. The surrounding air temperature of the system is also studied in the simulation. Following the verification, LED system with and without rectangular fixture are simulated and compared. The model without fixture shows better thermal results. The flow trajectory plot shows the difference in air convection with and without fixture. The simulation shows fixture disrupts the natural convection in the chamber.","PeriodicalId":198881,"journal":{"name":"Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114947820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Mu-GSIM: A mutation testing simulator on GPUs Mu-GSIM:基于gpu的突变测试模拟器

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-10-24 DOI: 10.1109/ASQED.2013.6643604

J. G. Tong, M. Boule, Z. Zilic

引用次数: 1

A 2.93μW 8-bit capacitance-to-RF converter for movable laboratory mice blood pressure monitoring 一种用于移动实验小鼠血压监测的2.93μW 8位电容-射频转换器

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-10-24 DOI: 10.1109/ASQED.2013.6643590

Ka-Meng Lei, Pui-in Mak, M. Law, R. Martins

引用次数: 0

Repairing of faulty TSVs using available number of multiplexers in 3D ICs 使用3D集成电路中可用的多路复用器修复故障的tsv

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-10-24 DOI: 10.1109/ASQED.2013.6643579

S. Roy, S. Chatterjee, C. Giri, H. Rahaman

引用次数: 3

A robust and energy efficient pulse generator for ultra-wide voltage range operations 一个强大的和节能的脉冲发生器，用于超宽电压范围的操作

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-10-24 DOI: 10.1109/ASQED.2013.6643568

Sebastien Bernard, D. Bol, A. Valentian, M. Belleville, J. Legat

引用次数: 4