基于纳米级CMOS技术的低功耗设计优化时钟门控单元

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-10-24 DOI:10.1109/ASQED.2013.6643569

Aniryudh Reddy Durgam, K. Choi

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引用次数: 4

摘要

讨论了一种针对高性能低功耗设计进行优化的新型时钟门控单元(CGC)。分析了传统的CGC以及之前提出的其他低功耗CGC实现。提出了新的CGC拓扑，并在动态时钟功率、漏损、面积和时序方面与之前介绍的拓扑进行了比较。

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Optimized clock gating cell for low power design in nanoscale CMOS technology

This paper discusses a novel clock gating cell (CGC) optimized for high performance and low power design. The conventional CGC is analyzed along with other low power implementations of the CGC that have previously been proposed. The new CGC topology is proposed and compared to the topologies previously introduced in terms of dynamic clock power, leakage, area and timing.

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Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)

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