Totally self-checking (TSC) VLSI circuits using Scalable Error Detection Coding (SEDC) technique

Abstract

Integrated circuits fabricated in deep sub-micron technology are vulnerable to intermittent or transient faults which are the predominant cause of system failures. With continued scaling, operating voltage levels have reduced and resultant decrease in noise margins, the possibility of transient faults is likely to increase. Also, during operation in adverse environments, transient faults occur upon exposure to ionizing radiations and neutron effects. These faults manifest themselves as unidirectional errors. The ability to operate in the intended manner even in the presence of faults is an important objective of all electronic systems. Totally Self-checking (TSC) circuits permit online detection of hardware faults. The Scalable Error Detection Coding (SEDC) technique used to design self-checking circuits with faster execution and lesser latency overhead for use in fault-tolerant VLSI circuits is presented. SEDC technique is formulated and architecture is designed in such a way that for any input binary data length, only area is scaled, with a constant latency of two logic gates and requires only a single clock cycle for generating SEDC code. It is shown that the proposed SEDC technique is found to be significantly efficient than the existing unidirectional error detection techniques in terms of speed, latency, area and achieving 100% error detection.