Improved test methodology for multi-clock domain SoC ATPG testing

Abstract

This paper proposes a test strategy for improving SoC ATPG testing. On-chip clock controller (OCC) is used to yield better at-speed test coverage and pattern generation. In addition, clock gating structure, coupled with virtual clock grouping constraint is implemented to guide stuck-at ATPG generation process. The proposed solution enables fewer ATPG generation iteration which helps to reduce test pattern count and optimize ATPG run time.