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Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)最新文献

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External loopback testing on high speed serial interface 高速串行接口的外部环回测试
Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-10-24 DOI: 10.1109/ASQED.2013.6643578
L. Shen
{"title":"External loopback testing on high speed serial interface","authors":"L. Shen","doi":"10.1109/ASQED.2013.6643578","DOIUrl":"https://doi.org/10.1109/ASQED.2013.6643578","url":null,"abstract":"Testing for high speed links have been, and will continue to be, primarily based on checking their conformance to the specifications and performance testing due to the lack of industry analog fault models. However, with the increased diversity of features to support new transceiver protocols, specification testing on high speed serial interface (HSSI) is becoming increasingly difficult and costly. Techniques like design-for-testability (DFT) have been applied to overcome some of these challenges. In this paper, the author presents case studies of one of the most common DFT techniques for HSSI testing, namely, external loopback. Firstly, the different flavors of loopback available in industry are briefly mentioned together with their usage. Next, the need for external loopback engagement in HSSI test strategy is described. This is then followed by the explanation of the external loopback circuitry on device-under-test (DUT) card and test methods for supporting HSSI buffer level testing that are implemented on transceiver based FPGA product. This paper also provides summary from silicon experiences and directions for future improvement.","PeriodicalId":198881,"journal":{"name":"Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126769566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Multiobjective evolutionary approach to silicon solar cell design optimization 硅太阳能电池设计优化的多目标进化方法
Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-10-24 DOI: 10.1109/ASQED.2013.6643586
Wen-Tsung Huang, Chieh-Yang Chen, Yu-Yu Chen, Sheng-Chia Hsu, Yiming Li
{"title":"Multiobjective evolutionary approach to silicon solar cell design optimization","authors":"Wen-Tsung Huang, Chieh-Yang Chen, Yu-Yu Chen, Sheng-Chia Hsu, Yiming Li","doi":"10.1109/ASQED.2013.6643586","DOIUrl":"https://doi.org/10.1109/ASQED.2013.6643586","url":null,"abstract":"In this study, we implement a device simulation-based multi-objective evolutionary algorithm (MOEA) for the optimal design of silicon solar cells. The short-circuited current, the open-circuited voltage, and the conversion efficiency are calculated and used to evaluate the fitness score and access the evolutionary quality of designing parameters via the implemented non-dominating sorting genetic algorithm in the unified optimization framework. Designing parameters, the material and structural parameters are simultaneously optimized for the explored solar cells. Our device simulation-based MOEA methodology is useful, compared with the conventional genetic algorithm, in the solar cell design optimization.","PeriodicalId":198881,"journal":{"name":"Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134394025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Congestion-oriented approach in placement for analog and mixed-signal circuits 面向拥塞的模拟和混合信号电路布置方法
Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-10-24 DOI: 10.1109/ASQED.2013.6643571
Hongxia Zhou, Chiu-Wing Sham, Hailong Yao
{"title":"Congestion-oriented approach in placement for analog and mixed-signal circuits","authors":"Hongxia Zhou, Chiu-Wing Sham, Hailong Yao","doi":"10.1109/ASQED.2013.6643571","DOIUrl":"https://doi.org/10.1109/ASQED.2013.6643571","url":null,"abstract":"Placement design is an essential step in VLSI design and the interaction between different modules makes it a complex process, especially for the integration of analog and mixed-signal circuits. The satisfactory placements of these circuits can be achieved by considering a series of constraints such as symmetry, and general placement constraints-alignment, abutment, preplace, boundary, range and maximum separation. Additionally, the placement result determines the routability of the subsequent routing work. Hence, routability is another important issue that should be considered during the placement phase. In this paper, we propose a new approach which expands the size of certain modules by analyzing the net congestion probability in respect of routability and satisfying the mentioned constraints during the placement process for analog and mixed-signal circuits. Experimental results demonstrate the effectiveness and feasibility of our approach in solving the routability-driven placement problem.","PeriodicalId":198881,"journal":{"name":"Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124708038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
High-quality data assignment to hierarchical memory organizations for multidimensional signal processing 高质量的数据分配到分层存储器组织用于多维信号处理
Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-10-24 DOI: 10.1109/ASQED.2013.6643570
F. Balasa, I. Luican, Doru V. Nasui
{"title":"High-quality data assignment to hierarchical memory organizations for multidimensional signal processing","authors":"F. Balasa, I. Luican, Doru V. Nasui","doi":"10.1109/ASQED.2013.6643570","DOIUrl":"https://doi.org/10.1109/ASQED.2013.6643570","url":null,"abstract":"In real-time data-dominated communication and multimedia processing applications, data transfer and storage significantly influence, if not dominate, all the major cost parameters of the design space - namely power consumption, performance, and chip area. Multi-layer memory hierarchies are used to reduce the energy consumption, but also to enhance the system performance. The energy-aware optimization of a hierarchical memory architecture implies the addition of layers of smaller and faster memories used to store the intensely-used data, in order to better exploit the non-uniform memory accesses. This paper presents an electronic design automation (EDA) methodology for energy-efficient signal assignment to the memory layers of a hierarchical storage organization. This approach starts from the behavioral specification of a given application and, employing algebraic techniques specific to the data-dependence analysis used in modern compilers, identifies those parts of (multidimensional) arrays intensely accessed. Tested on a two-layer memory hierarchy, this EDA methodology led to savings of storage energy consumption from 40 % to over 60 % relative to the energy used in the case of flat memory designs.","PeriodicalId":198881,"journal":{"name":"Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127419183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Methods of optimized via design for higher channel bandwidth 针对更高信道带宽的优化通孔设计方法
Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-10-24 DOI: 10.1109/ASQED.2013.6643582
Y. Fei
{"title":"Methods of optimized via design for higher channel bandwidth","authors":"Y. Fei","doi":"10.1109/ASQED.2013.6643582","DOIUrl":"https://doi.org/10.1109/ASQED.2013.6643582","url":null,"abstract":"This paper analyzes the ability of an optimized via design to achieve higher channel bandwidth by minimizing the impedance discontinuity of a high speed serial link above 5Gbps owing to the parasitic capacitive effect of vias on a single Printed Circuit Board (PCB). The methods of optimized via design are back-drilling plated through hole, removing unused pads and increasing anti-pad clearance [1]. Different via features and their impact are studied in 3D model extraction using EMPro software from Agilent, and simulations are done using Advanced Design System (ADS) where the measurement of insertion loss, time domain reflectometry (TDR) and eye diagrams are used. Subsequently, the simulation results are correlated with measurement results from a prototype PCB.","PeriodicalId":198881,"journal":{"name":"Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)","volume":"09 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128324585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Design and simulation of Clamped-Clamped and Clamped-Free resonators 箝位-箝位和无箝位谐振器的设计与仿真
Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-10-24 DOI: 10.1109/ASQED.2013.6643564
Ahmad Anwar Zainuddin, J. Karim, A. Nordin, M. S. Pandian, K. Sheroz
{"title":"Design and simulation of Clamped-Clamped and Clamped-Free resonators","authors":"Ahmad Anwar Zainuddin, J. Karim, A. Nordin, M. S. Pandian, K. Sheroz","doi":"10.1109/ASQED.2013.6643564","DOIUrl":"https://doi.org/10.1109/ASQED.2013.6643564","url":null,"abstract":"To date, there have been interests in designing the Micro-Electro-Mechanical System (MEMS) integrated with Complementary Metal-Oxide Semiconductor (CMOS) resonator for RF integrated circuits. This work presents the design of Clamped-Clamped (CC) and Clamped-Free (CF) beam resonators. These resonators provide on-chip low cost solutions for devices with much reduced chip area, besides having considerably reduced insertion losses due to nonexistent external bond wires. They can be integrated with amplifiers to form oscillators for generating clocks in the 2MHz and 20MHz range. The resonators require DC voltage maximally 10V for Clamped-Clamped and 7V for Clamped-free and 100mV AC voltage to electrostatically actuate the resonator's beams. The actuation is simulated and measured using Finite Element modeling software of COMSOL to obtain optimum design parameters. This paper makes a comparative review of different models for evaluating the designed resonator's performance in terms of resonance frequency under given pull-in voltage, and appropriate displacement.","PeriodicalId":198881,"journal":{"name":"Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)","volume":"693 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122979838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An electrical study of differential clock die-to-die interconnection in multi-chip packages 多芯片封装中差分时钟模对模互连的电学研究
Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-10-24 DOI: 10.1109/ASQED.2013.6643587
T. M. Keen, Tan Wei Jern
{"title":"An electrical study of differential clock die-to-die interconnection in multi-chip packages","authors":"T. M. Keen, Tan Wei Jern","doi":"10.1109/ASQED.2013.6643587","DOIUrl":"https://doi.org/10.1109/ASQED.2013.6643587","url":null,"abstract":"This paper presents an electrical study on die-to-die interconnect, differential clock signals in MCPs. The paper seeks to tackle the issues caused by shorter and denser interconnection in combination with an ever-decreasing z-height profile. The proposed methods focus on buffer and channel design on existing or new signaling. Of note, they maintain a fair amount of design flexibility, while not jeopardizing overall margins. The methods primarily mitigate harmful ringing, ledge effects and excessively slow slew rates in the monotonic region in both MCP and discrete solutions. Ultimately, this translates into a shift in line with recent platforms' sleek and thin form factor and in turn, a cost saving benefit.","PeriodicalId":198881,"journal":{"name":"Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125687916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 128-phase delay-locked loop with cyclic VCDL 具有循环VCDL的128相延迟锁相环
Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-10-24 DOI: 10.1109/ASQED.2013.6643555
Chien-Hung Kuo, Yu-Chieh Ma
{"title":"A 128-phase delay-locked loop with cyclic VCDL","authors":"Chien-Hung Kuo, Yu-Chieh Ma","doi":"10.1109/ASQED.2013.6643555","DOIUrl":"https://doi.org/10.1109/ASQED.2013.6643555","url":null,"abstract":"A multiphase delay-locked loop with cyclic voltage controlled delay line is presented in this paper. The 128 output phases can be simultaneously produced by the 16-delay units of VCDL. The presented multi-phase DLL is realized by CMOS 90 nm 1P9M process. The total power consumption is 9.2 mW at the supply voltage of 1.2 V and the operational frequency of 92.16 MHz.","PeriodicalId":198881,"journal":{"name":"Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)","volume":"2016 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125731667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Online error detection in SRAM based FPGAs using Scalable Error Detection Coding 基于可扩展错误检测编码的SRAM fpga在线错误检测
Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-10-24 DOI: 10.1109/ASQED.2013.6643606
Zahid Ali Siddiqui, Jeong-A Lee
{"title":"Online error detection in SRAM based FPGAs using Scalable Error Detection Coding","authors":"Zahid Ali Siddiqui, Jeong-A Lee","doi":"10.1109/ASQED.2013.6643606","DOIUrl":"https://doi.org/10.1109/ASQED.2013.6643606","url":null,"abstract":"SRAM based devices are more susceptible to unidirectional errors when exposed to radiations. This paper presents an error detection scheme for detecting errors in SRAM cells of FPGA. This proposed Scalable Error Detection Coding (SEDC) scheme is capable of detecting 100% unidirectional errors. SEDC scheme partitions the data into segments of 2-, 3- and 4-bits data and encodes these segments using SEDC codes, in parallel fashion. The programming device generates the SEDC check bits and stores them on the FPGA's SRAM cells. A high speed, compact and easily scalable online SEDC check bit generator generates the SEDC check bits, which are compared with the pre-stored check bits during circuit operation. All unidirectional errors in SRAM cells, caused by cosmic radiations, are detected. The proposed technique achieves significant improvement in area as well as speed over Berger & simple TMR technique for the same application.","PeriodicalId":198881,"journal":{"name":"Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120984657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Rapid search of Pareto fronts using D-logic exploration during multi-objective tradeoff of computation intensive applications 计算密集型应用中基于d -逻辑探索的Pareto前沿快速搜索
Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) Pub Date : 2013-10-24 DOI: 10.1109/ASQED.2013.6643573
A. Sengupta, V. Mishra, Pallabi Sarkar
{"title":"Rapid search of Pareto fronts using D-logic exploration during multi-objective tradeoff of computation intensive applications","authors":"A. Sengupta, V. Mishra, Pallabi Sarkar","doi":"10.1109/ASQED.2013.6643573","DOIUrl":"https://doi.org/10.1109/ASQED.2013.6643573","url":null,"abstract":"Design space exploration in architectural synthesis is a complicated process of balancing multiple orthogonal issues such as a) decreasing the time of exploration as well as enhancing the quality of final solution b) optimizing conflicting objectives such as reducing the power requirement (or alternatively area requirement) as well as augmenting the performance of the final circuit. This paper presents a novel methodology using Dominance criterion (D-logic) to effectively handle the problem of DSE based on either power-execution time tradeoff (with area as an optimization criteria) or area-execution time tradeoff (with power as an optimization criteria). The proposed work introduces novel D-logic mathematical models for three parameters viz. power, execution time and area that deterministically prune the vast design space into a subset of valid design variants without compromising the speed and quality of the design variances. The proposed method is several orders of magnitude faster and superior in terms of searching Pareto fronts and identifying an optimal solution than recent genetic based DSE technique where average improvement in quality of results (QoR) achieved is > 9 % (in terms of power and execution time) and average reduction in exploration time is > 90 %.","PeriodicalId":198881,"journal":{"name":"Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114892064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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