A low-power circuit architecture for transistor electrical overstress (EOS) protection

Abstract

As the transistor dimension keeps shrinking following trend predicted by Moore's Law, the voltage that transistor can sustain reliably is also reducing. For certain serial interface protocols (like the ubiquitous Universal Serial Bus (USB)) and some legacy input/output interfaces, high voltages like 1.8V, 3.3V and even 5.0V are still being used for protocol compliance. It is costly in silicon fabrication to provide transistors with different gate-oxide thickness to cater for various high voltage and speed requirements. In order to minimize the type of gate oxide thickness in advanced silicon process, circuit innovation is usually required to enable transistor to operate with voltage higher than its reliability limit, yet protected from electrical overstress (EOS). This paper discusses a new circuit architecture that is able to detect voltage source as well as to switch between external source and internal biasing voltage to ensure all transistors operating with high voltage are not exposed to the voltage limit. This circuit is low power in nature since it does not consume static current. By having this protection scheme, this would enable the use of transistor to support high-voltage application without incurring cost of having additional thicker gate-oxide transistor. In terms of application, this architecture can be used in integrated chip design involving various high-voltage supplies.