Logic emulation with forced assertions: A methodology for rapid functional verification and debug

Abstract

To improve debugging turnaround time of complex System-on-chip (SoC) designs on FPGA based logic emulation systems, it is important to minimize the iterations through design recompilation or FPGA reconfiguration process for validating repeated debugging changes. This paper presents a methodology for modeling debugging changes in terms of standalone assertion statements and evaluating their effect by running emulation without requiring any design modification or recompilation step, during emulation based debug. The set of assertions representing debugging changes are transformed into a set of constraints that are directly programmed into the emulator and an associated logic analyzer. When emulation is resumed from a bug-free state, these constraints are enforced by automatically forcing necessary signals to desired values, according to the specified assertions. Multiple debugging changes can thus be verified before eventually porting the fixes to design RTL followed by recompilation and emulation rerun. The proposed methodology also facilitates block based SoC development, by allowing a designer to enforce the correct functional behavior of some other block whose output affects the behavior of the block he is working on. Application of the proposed debugging system to debugging of real industry standard designs has been seen to reduce debugging turn-around time significantly.