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Proceedings of the Sixth Great Lakes Symposium on VLSI最新文献

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Clock buffer placement algorithm for wire-delay-dominated timing model 线延迟主导时序模型的时钟缓冲器放置算法
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497610
M. Edahiro, R. Lipton
{"title":"Clock buffer placement algorithm for wire-delay-dominated timing model","authors":"M. Edahiro, R. Lipton","doi":"10.1109/GLSV.1996.497610","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497610","url":null,"abstract":"A clock buffer placement algorithm is proposed for future technologies in which wire delay dominates signal delay. In such technologies, buffers need to be placed so as to minimize the maximum wire delay. We formulate the problem into a non-linear programming, and solve it by an iteration method with a randomized technique. We applied our buffer placement algorithm with a zero-skew router to several benchmark data, and show that our algorithm achieves 30% less delay time than a H-tree based algorithm.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"303 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132706931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Low-power implementation of discrete cosine transform 离散余弦变换的低功耗实现
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497615
E. Farag, M. Elmasry
{"title":"Low-power implementation of discrete cosine transform","authors":"E. Farag, M. Elmasry","doi":"10.1109/GLSV.1996.497615","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497615","url":null,"abstract":"The demand for multimedia mobile terminals has created a need for low power implementation of video compression algorithms. In this paper we consider different implementations for the discrete cosine transform. The effect of pipelining and parallelism on reducing the power dissipation is considered for fast discrete cosine transform algorithms, as well as ROM-based algorithms.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"149 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132152125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Delay hazards in complex gate based speed independent VLSI circuits 基于速度无关的复杂栅极VLSI电路中的延迟危害
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497631
N. Tabrizi, M. Liebelt, K. Eshraghian
{"title":"Delay hazards in complex gate based speed independent VLSI circuits","authors":"N. Tabrizi, M. Liebelt, K. Eshraghian","doi":"10.1109/GLSV.1996.497631","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497631","url":null,"abstract":"Although speed independent VLSI circuit design is supported by rich theory at higher levels, it suffers from the lack of an area efficient robust transistor level implementation technique. In this paper we introduce safe cells based on which well-formed STGs can be implemented free of (delay) hazards with no unrealistic assumptions about physical gates. Although this technique still compromises chip area for the sake of preventing hazards, we show that it may achieve a significant area gain in comparison with the two-phase RS-implementation method, which is one of the few true speed independent implementation techniques that we are aware of so far. Delay hazards are then analysed in complex gate based speed independent circuits and hence theorems are developed to identify a subclass of delay hazards.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128273401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A global mode instruction minimization technique for embedded DSPs 嵌入式dsp的全局模式指令最小化技术
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497586
G. Grewal
{"title":"A global mode instruction minimization technique for embedded DSPs","authors":"G. Grewal","doi":"10.1109/GLSV.1996.497586","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497586","url":null,"abstract":"This paper addresses the problem of minimizing mode setting instructions for embedded DSPs. Many such processors use a state register to control the mode of ALU operations (e.g., sign extension, round, and shift). Often two or more modes can be changed by a single instruction. A method is given to determine the minimum number of instructions needed to properly set modes, assuming a schedule has been determined. Our approach models the problem as a minimum cover, and is not limited to a basic block. Block frequency information is exploited to encourage mode changes in less frequently executed blocks whenever possible. Special attention is given to the proper optimization of loops.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130478289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A high speed, real-to-quadrature converter with filtering and decimation 具有滤波和抽取功能的高速实正交变换器
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497628
L. Desormeaux, V. Szwarc, J. Lodge
{"title":"A high speed, real-to-quadrature converter with filtering and decimation","authors":"L. Desormeaux, V. Szwarc, J. Lodge","doi":"10.1109/GLSV.1996.497628","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497628","url":null,"abstract":"The design of a high speed, real-to-quadrature converter chip set with filtering, decimation, built-in self-test (BIST), and IEEE 1149.1 based boundary scan will be presented. The 15,000 gate application specific integrated circuit (ASIC) implemented in 1.5 /spl mu/m CMOS gate array technology has 3 half-band filters with 3, 7, and 11 taps which can be cascaded in a number of combinations. The intended ASIC application is the processing of narrowband radio signals at IF frequencies. The paper addresses the ASIC's functionality, VLSI implementation and test methodology, and provides both simulation and test data.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130157142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A hierarchical approach for power reduction in VLSI chips VLSI芯片中降低功耗的分层方法
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497617
P. Arunachalam, J. Abraham, M. d'Abreu
{"title":"A hierarchical approach for power reduction in VLSI chips","authors":"P. Arunachalam, J. Abraham, M. d'Abreu","doi":"10.1109/GLSV.1996.497617","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497617","url":null,"abstract":"This paper presents a new mechanism for power analysis and reduction that exploits the hierarchical nature of circuits. A number of mechanisms have been proposed for power reduction, but they do not offer solutions in all cases. An activity-based reduction technique is presented where the clock is turned off for entire modules or sub-modules hierarchically when that portion of the circuit is not in use. Behavioral constraints are used to determine when a portion of the circuit is in use. The method shown is a top-down approach independent of the technology used during fabrication of the chip. Experimental results indicate that this method will result in a considerable reduction in power.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132629680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Macromodeling C- and RC-loaded CMOS inverters for timing analysis 宏建模C和rc负载CMOS逆变器的时序分析
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497632
A. Kayssi
{"title":"Macromodeling C- and RC-loaded CMOS inverters for timing analysis","authors":"A. Kayssi","doi":"10.1109/GLSV.1996.497632","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497632","url":null,"abstract":"Timing macromodels for a CMOS inverter loaded by a capacitor or by a series-resistor shunt-capacitor circuit are derived and verified. The macromodel for the capacitive load case is a simple analytical function of a single variable which combines input wave shape, capacitive load, and transistor drive. The model for the RC case is a combination of lookup table and analytical function yielding excellent accuracy to within 5% of detailed circuit simulation.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115940089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Synthesis of real-time recursive DSP algorithms using multiple chips 综合多芯片DSP实时递归算法
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497584
Duen-Jeng Wang, Y. Hu
{"title":"Synthesis of real-time recursive DSP algorithms using multiple chips","authors":"Duen-Jeng Wang, Y. Hu","doi":"10.1109/GLSV.1996.497584","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497584","url":null,"abstract":"In this paper, the problem of synthesizing real-time recursive DSP algorithms with fixed interprocessor communication delay is addressed. The effects of the communication delay to the initiation interval and number of chips are studied. We differentiate our problem from previous work in two parts. First, the DSP algorithms we consider are recurrence. Second, communication delay is considered. By modifying previously proposed scheduling and allocation algorithm, we are able to derive an implementation if it exists under the given real-time and area constraints. Some experiments have been made and results are very promising.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"405 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122194153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 3 V-50 MHz analog CMOS current-mode high frequency filter with a negative resistance load 一个3 V-50 MHz模拟CMOS电流模式高频滤波器与负电阻负载
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497630
J. Hyun, K. Yoon
{"title":"A 3 V-50 MHz analog CMOS current-mode high frequency filter with a negative resistance load","authors":"J. Hyun, K. Yoon","doi":"10.1109/GLSV.1996.497630","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497630","url":null,"abstract":"A low voltage analog CMOS current-mode continuous-time high frequency filter with a negative resistance load (NRL) is proposed. To design a current integrator, we use a modified simple current mirror with a NRL to increase the output resistance. The current integrator is designed to have the frequency behavior enhancement and operate in low voltage by employing a simple mirror structure and diode connected input transistor. The third order Butterworth low pass filter using a current integrator is synthesized and simulated with a 1.5 /spl mu/m n-well process. Simulation result shows cutoff frequency of 50 MHz and power consumption of 2.4 mW/pole with a 3 V power supply.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132140565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design and VLSI implementation of a unified synapse-neuron architecture 统一突触-神经元架构的设计与VLSI实现
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497624
H. Djahanshahi, M. Ahmadi, G. Jullien, W. Miller
{"title":"Design and VLSI implementation of a unified synapse-neuron architecture","authors":"H. Djahanshahi, M. Ahmadi, G. Jullien, W. Miller","doi":"10.1109/GLSV.1996.497624","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497624","url":null,"abstract":"We describe the design and VLSI implementation of a unified synapse-neuron architecture for multi-layer neural networks. A new hybrid building block proposed for this purpose is formed by integrating a partial S-shape neural nonlinearity within a Multiplying DAC synapse. MDAC synapse contains modifications to simplify sign-bit circuit. Small analog circuits generate a distributed S-shape neural function by combining quadratic characteristics of four MOS transistors. The proposed modular neural network architecture features design simplicity and scalability, area efficiency, reduced interconnection problem, improved robustness and digital programmability. Based on the proposed scheme, we have considerably increased the synaptic density in the improved version of a programmable optically-coupled neural network.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132225748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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