A hierarchical approach for power reduction in VLSI chips

Abstract

This paper presents a new mechanism for power analysis and reduction that exploits the hierarchical nature of circuits. A number of mechanisms have been proposed for power reduction, but they do not offer solutions in all cases. An activity-based reduction technique is presented where the clock is turned off for entire modules or sub-modules hierarchically when that portion of the circuit is not in use. Behavioral constraints are used to determine when a portion of the circuit is in use. The method shown is a top-down approach independent of the technology used during fabrication of the chip. Experimental results indicate that this method will result in a considerable reduction in power.