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Proceedings of the Sixth Great Lakes Symposium on VLSI最新文献

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Chip pad migration is a key component to high performance MCM design 芯片垫迁移是高性能MCM设计的关键组成部分
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497601
James Loy, A. Garg, M. Krishnamoorthy, J. McDonald
{"title":"Chip pad migration is a key component to high performance MCM design","authors":"James Loy, A. Garg, M. Krishnamoorthy, J. McDonald","doi":"10.1109/GLSV.1996.497601","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497601","url":null,"abstract":"As Multichip Modules (MCMs) evolve from niche solutions to necessary ingredients of high performance computing systems, this change must be reflected in the associated CAD tools for MCM system design. Given the transmission velocities of modern thin film substrates, conventional design techniques where chips are developed in isolation from the substrate fall short of producing optimal solutions. Critical to the success of these tools is the ability to influence chip pad placement. Our research indicates that an integrated chip/MCM codesign environment should be established. MCM CAD tools must provide advice for and accommodate an interactive pad migration facility, where chip designers are provided recommended signal pad locations that contribute to the optimization of the overall system.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122744115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A provably good moat routing algorithm 一个可证明的好的护城河路由算法
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497599
J. L. Ganley, J. Cohoon
{"title":"A provably good moat routing algorithm","authors":"J. L. Ganley, J. Cohoon","doi":"10.1109/GLSV.1996.497599","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497599","url":null,"abstract":"Moat routing is the routing of nets between the input/output pads and the core circuit. In this paper, it is proved that moat routing is NP-complete under the routing model in which there are no vertical conflicts and doglegs are disallowed (i.e., every net is routed within a single track). This contrasts with the fact that channel routing is efficiently solvable under these restrictions. The paper then presents an approximation algorithm for moat routing that computes moat routing solutions that are guaranteed to use at most four times the optimal number of tracks. Empirical results are presented indicating that for a number of industrial benchmarks, the algorithm produces solutions that are near optimal and that use significantly fewer tracks than previous moat routing strategies.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129661207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
FPGA-based high performance page layout segmentation 基于fpga的高性能页面布局分割
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497588
N. Ratha, Anil K. Jain, D. Rover
{"title":"FPGA-based high performance page layout segmentation","authors":"N. Ratha, Anil K. Jain, D. Rover","doi":"10.1109/GLSV.1996.497588","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497588","url":null,"abstract":"A page layout segmentation algorithm for locating text, background and halftone areas is presented. The algorithm has been implemented on Splash 2-an FPGA-based array processor. The speed as determined by the Xilinx synthesis tools projects an application speed of 5 MHz. For documents of size 1,024/spl times/1,024 pixels, a significant speedup of two orders of magnitude compared to a SparcStation 20 has been achieved.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133264802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A CMOS VLSI implementation of an N/spl times/N multiplexing circuitry for ATM applications 一种用于ATM应用的N/spl倍/N复用电路的CMOS VLSI实现
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497629
M. Rizkalla, R. L. Aldridge, N. Khan, H. Gundrum
{"title":"A CMOS VLSI implementation of an N/spl times/N multiplexing circuitry for ATM applications","authors":"M. Rizkalla, R. L. Aldridge, N. Khan, H. Gundrum","doi":"10.1109/GLSV.1996.497629","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497629","url":null,"abstract":"A non internal blocking ATM packet switching network using CMOS technology has been developed for an N/spl times/N switch. A multiplexing circuitry with 32 inputs was designed and implemented using simple logic gates. The development has utilized an interconnection network of 1/spl times/32 parallel expander circuits. The control unit consisting of serial shift registers and latches to keep the destination path open for the length of the packet, were designed using MAGIC software and simulated by IRSIM. As low as 5 ns delay was estimated by the 1/spl times/32 expander circuit, while the clock generated by the combinational circuit for latching showed a delay of 190 ns. The system has been fabricated using MOSIS services, and as minimum of 5 ns delay was measured between the input and output nodes of the switching circuit.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124549418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Resource constrained algebraic transformation for loop pipelining 循环流水线的资源约束代数变换
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497585
Jian-Feng Shi, L. Chao
{"title":"Resource constrained algebraic transformation for loop pipelining","authors":"Jian-Feng Shi, L. Chao","doi":"10.1109/GLSV.1996.497585","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497585","url":null,"abstract":"Loop pipelining can be applied to a cyclic data-flow graph to reduce the iteration bound, which is the maximum computation-time-to-delay ratio among all the cycles in the data flow graph. Algebraic transformations can reduce the iteration bound substantially. However, resource constrained algebraic transformations for loop pipelining remains a hard problem because of the inherent nature of loop pipelining. In this paper, we propose a new method based on distribution graphs to solve this problem. A novel algorithm for algebraic transformation with resource constraints is provided, which works for non-pipelined schedules as well. Experimental results show that our algorithm is promising.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125433061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A parameterized index-generator for the multi-dimensional interleaving optimization 多维交错优化的参数化索引生成器
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497595
N. Passos, E. Sha
{"title":"A parameterized index-generator for the multi-dimensional interleaving optimization","authors":"N. Passos, E. Sha","doi":"10.1109/GLSV.1996.497595","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497595","url":null,"abstract":"The novel optimization technique for the design of application specific integrated circuits of multi-dimensional problems, called multi-dimensional interleaving consists of an expansion and compression of the iteration space. It guarantees that all functional elements of a circuitry can be executed simultaneously, and no additional memory queues proportional to the problem size are required. Such technique, that considers the parallelism inherent to multi-dimensional problems, depend on loop transformations that require a new execution sequence of the loop. This study presents a new approach on synthesizing multidimensional (nested) loops, where pre-processor tools can rewrite the instructions in such a way to accommodate the required changes in the optimized design. This new approach is expected to improve the design cycle by including multidimensional signal processing and other common applications in the scope of the synthesis tools.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123347737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Performance-driven interconnect global routing 性能驱动的互连全局路由
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497608
Dongsheng Wang, E. Kuh
{"title":"Performance-driven interconnect global routing","authors":"Dongsheng Wang, E. Kuh","doi":"10.1109/GLSV.1996.497608","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497608","url":null,"abstract":"In this paper, we propose a global routing algorithm for multi-layer building-block layouts. The algorithm is based on successive rip up and rerouting while satisfying edge capacity constraints as well as achieving higher routability and good routing flexibility. The initial solution consists of nets routed independently by the SERT-C algorithm which minimizes the Elmore delay at critical sink of a Steiner tree. Then, all the nets with the most congested edge, i.e., the edge with maximum flow, are ripped up and rerouted by using an iterative hierarchical approach. For each iteration, a window is specified according to the span of the ripped-up nets or an upper bound if the span is too large. Rerouting is done hierarchically within the window by using integer programming to optimize the flow uniformity. The algorithm terminates when the flow uniformity can not be further improved. The algorithm has been implemented and interfaced with a placement tool. Experiments show that the algorithm can improve the flow uniformity by 19% to 97%. The final results include the number of routing layers needed to complete the routing. Thus, the method is also useful in determining the required number of layers for pack aging design using multi-chip models.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"291 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115927896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
TROY: a tree based approach to logic synthesis and technology mapping TROY:一种基于树的逻辑合成和技术映射方法
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497618
W. Nöth, Uwe Hinsberger, Reiner Kolla
{"title":"TROY: a tree based approach to logic synthesis and technology mapping","authors":"W. Nöth, Uwe Hinsberger, Reiner Kolla","doi":"10.1109/GLSV.1996.497618","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497618","url":null,"abstract":"In this paper we present a new approach to the synthesis of combinational circuits and the mapping of standard gates like NAND, NOR, AOI and OAI with arbitrary number of inputs. Our method is based on the provable optimal synthesis of the fan-out-free regions of a circuit, represented as normal AND-OR-trees. Normal AND-OR-trees enable TROY to rebalance the regions with respect to delay without loosing area and lead to a much larger search space than that used by tree matching. Fast heuristics derived from the optimal approach yield significantly faster results than SIS on many standard benchmark circuits.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115120783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
An efficient multiple scan chain testing scheme 一种高效的多扫描链测试方案
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497636
Zaifu Zhang, R. McLeod
{"title":"An efficient multiple scan chain testing scheme","authors":"Zaifu Zhang, R. McLeod","doi":"10.1109/GLSV.1996.497636","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497636","url":null,"abstract":"In this paper an improved multiple scan chain testing scheme to enhance stuck-at and delay fault testing is proposed. With judicial selection of taps from an n stage CA generator, correlation within a multiple input scan chain is reduced. Adopting the multiple scan chains fed by the selected taps of the CA generator also eases the difficulty of arranging shift register latches (SRLs) for scan based pseudo-exhaustive stuck-at fault testing.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123333739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Self-timed mesochronous interconnection for high-speed VLSI systems 高速VLSI系统的自定时同步互连
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497606
Seokjin Kim, R. Sridhar
{"title":"Self-timed mesochronous interconnection for high-speed VLSI systems","authors":"Seokjin Kim, R. Sridhar","doi":"10.1109/GLSV.1996.497606","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497606","url":null,"abstract":"Self-timed mesochronous interconnection scheme is presented for the interface between synchronous modules. It consists of a self-timed FIFO and a local clock control circuit placed between synchronous modules. The self-timed FIFO receives a data stream and holds it until the first data is synchronized at the receiving module. After the synchronization, the clock input to the receiving module is available through the local clock control circuit. The interconnection scheme operates regardless of the amount of the clock skew between the modules. An experimental design is presented that demonstrates the validity of the method.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129794689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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