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Proceedings of the Sixth Great Lakes Symposium on VLSI最新文献

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On double transition faults as a delay fault model 双过渡故障作为延迟故障模型的研究
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497634
I. Pomeranz, S. Reddy, J. Patel
{"title":"On double transition faults as a delay fault model","authors":"I. Pomeranz, S. Reddy, J. Patel","doi":"10.1109/GLSV.1996.497634","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497634","url":null,"abstract":"We define a new delay fault model, called the double transition fault model. Under this model, a fault is associated with a pair of lines and a pair of transitions on these lines. The model captures the effects of defects that increase the delays of two (or more) individual lines by an amount that causes the circuit to fail when signals are propagated through both lines. It thus provides a simplification of the path delay fault model, that does not suffer from the exponential behavior of this model. We propose a test generation procedure for double transition faults, based on reordering of a given test set for stuck-at faults. The procedure does not require enumeration of all double transition faults, and is thus applicable to circuits with large numbers of lines. We present experimental results of this procedure for several benchmark circuits.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"359 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124520722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A reprogrammable FPGA-based ATM traffic generator 基于可编程fpga的ATM流量发生器
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497589
P.P. Chul, B. Frantz
{"title":"A reprogrammable FPGA-based ATM traffic generator","authors":"P.P. Chul, B. Frantz","doi":"10.1109/GLSV.1996.497589","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497589","url":null,"abstract":"Markov modulated process is widely used to model ATM (Asynchronous Transmission Mode) traffic sources. We develop an approximation algorithm and design an FPGA (Field Programmable Gate Array) based circuit to generate cell trigger emulating this process. The design takes advantage of the reprogrammability of SRAM or E/sup 2/PROM FPGA. Instead of storing the process' various parameters in registers, our design \"hardwires\" these parameters into the circuitry and greatly simplifies the circuit complexity. Our testing circuit can be fitted into a moderate-sized FPGA chip and can generate up to 12 M triggers per second.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125073103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Formal verification of an ATM switch fabric using multiway decision graphs 使用多路决策图的ATM交换结构的正式验证
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497603
S. Tahar, Zijian Zhou, Xiaoyu Song, E. Cerny, M. Langevin
{"title":"Formal verification of an ATM switch fabric using multiway decision graphs","authors":"S. Tahar, Zijian Zhou, Xiaoyu Song, E. Cerny, M. Langevin","doi":"10.1109/GLSV.1996.497603","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497603","url":null,"abstract":"In this paper we present our results on formally verifying the implementation of an asynchronous transfer mode (ATM) network switching fabric using a new class of decision graphs, called Multiway Decision Graphs (MDG). The design we consider is in use for real applications in the Cambridge Fairisle network. We produced the description of the hardware implementation at different levels of abstraction. We then performed the verification of an abstract description model against the description of the gate-level implementation. Using this abstract model, we accomplished the verification of specific properties that reflect the behavior of the Fairisle ATM switch fabric.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126256791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Partitioning algorithms for corner stitching [VLSI] 角点拼接的分割算法[VLSI]
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497620
M.A. Lopez, D. Mehta
{"title":"Partitioning algorithms for corner stitching [VLSI]","authors":"M.A. Lopez, D. Mehta","doi":"10.1109/GLSV.1996.497620","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497620","url":null,"abstract":"We present two practical algorithms for partitioning circuit components represented by rectilinear polygons so that they can be stored using the L-shaped corner stitching data structure; i.e., our algorithms decompose a simple polygon into non-overlapping L-shapes and rectangles by using horizontal cuts only. The more general of our algorithms computes an optimal configuration for a wide variety of optimization functions, while the other computes a minimum configuration of rectangles and L-shapes. Both run in O(n+h log h) time, where n is the number of vertices in the polygon and h is the number of H-pairs. Experimental results on VLSI data demonstrate the gains in performance for corner stitching obtained by using our algorithms instead of traditional rectangular partitioning algorithms.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134258100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Recent developments in performance driven Steiner routing: an overview 性能驱动的斯坦纳路由的最新发展:概述
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497609
M. Borah, R. Owens, M. J. Irwin
{"title":"Recent developments in performance driven Steiner routing: an overview","authors":"M. Borah, R. Owens, M. J. Irwin","doi":"10.1109/GLSV.1996.497609","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497609","url":null,"abstract":"The contribution of interconnect delay to the stage delay of a circuit is increasing with scaling of the minimum feature size. At larger feature size the interconnect delay contribution was small and the driver resistance was very large compared to wire resistance. Consequently, a simple lumped model was sufficient for evaluating and optimizing circuit delay. However, with sub-micron processes, the contribution of interconnect delay dominates the stage delay and the wire resistance becomes noticeable, making the interconnect delay dependent on the routing topology. Hence it is becoming necessary to use a more accurate model for estimating and optimizing interconnect delay. This paper surveys the recent advancements in techniques for generating on-chip interconnect topology for optimizing circuit performance.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129351413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Simultaneous routing and buffer insertion for high performance interconnect 同时路由和缓冲区插入高性能互连
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497611
J. Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin
{"title":"Simultaneous routing and buffer insertion for high performance interconnect","authors":"J. Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin","doi":"10.1109/GLSV.1996.497611","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497611","url":null,"abstract":"We present an algorithm for simultaneously finding a rectilinear Steiner tree T and buffer insertion points into T. The objective of the algorithm is to minimize a cost function (e.g., total area or power) subject to given timing constraints on the sinks of the net. An interesting side-effect of our approach is that we are able to derive an entire cost/delay tradeoff curve for added flexibility. The solutions produced by the algorithm are optimal subject to the constraint that the routing topology be induced by a permutation on the sinks of the net. We show that high quality sink permutations can be derived from a given routing structure such as the minimum spanning tree. This derivation provides an error bound on the minimum area solution induced by the permutation. The effectiveness of our algorithm is demonstrated experimentally.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126873134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 63
CMOS transistor sizing for minimization of energy-delay product 最小化能量延迟积的CMOS晶体管尺寸
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497614
C. Tretz, C. Zukowski
{"title":"CMOS transistor sizing for minimization of energy-delay product","authors":"C. Tretz, C. Zukowski","doi":"10.1109/GLSV.1996.497614","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497614","url":null,"abstract":"In this paper, we revisit three of the well known optimization results in CMOS transistor sizing with the energy-delay product as a new metric. We study the absolute sizes of and the ratio between n-channel and p-channel transistor widths in uniform logic, the optimal distance between repeaters in an RC line, and the optimum number of inverter stages, along with their sizes, needed to drive a large load capacitance. Results, both theoretical and numerical, show that in general the optimum solutions for energy-delay lead to smaller designs than the ones obtained for minimum delay.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121771161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Timing and power optimization by gate sizing considering false path 考虑假路径的栅极尺寸的时序和功率优化
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497612
Guangqiu Chen, H. Onodera, K. Tamaru
{"title":"Timing and power optimization by gate sizing considering false path","authors":"Guangqiu Chen, H. Onodera, K. Tamaru","doi":"10.1109/GLSV.1996.497612","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497612","url":null,"abstract":"This paper introduces a new gate sizing approach for area and power optimization considering path sensitization. The approach selects a set of long paths from a combinational circuit by means of a performance optimization oriented heuristic path selection approach. The longest sensitizable path delay of the circuit can be restricted within the specified delay limit if we set the specified delay limit on these paths in an LP based iterative gate sizing process. Since the approach get rid of unnecessary delay constraints on long false paths, results with smaller circuit area or power dissipation is expected. Experiments on benchmark circuits show that the proposed approach can substantially reduce the circuit area and power dissipation by considering path sensitization for some false path dominated circuits.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125627559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A modular architecture for real time HDTV motion estimation with large search range 一种大搜索范围实时高清电视运动估计的模块化结构
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497626
Hangu Yeo, Y. Hu
{"title":"A modular architecture for real time HDTV motion estimation with large search range","authors":"Hangu Yeo, Y. Hu","doi":"10.1109/GLSV.1996.497626","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497626","url":null,"abstract":"A modular architecture with random access on-chip local memory for real-time motion estimation has been proposed. The random access on-chip local memory with simple address generation has been proposed to overcome the irregular data flow of the three-step search BMA. This architecture features simple interconnection with low memory bandwidth and throughput rate as high as 1/N block per clock cycle for an N/spl times/N block with the search range of d/sub m/=N/2-1 pixels with 100% processor utilization. By using a method called pipeline interleaving, this architecture offers a feasible solution for the Grand Alliance HDTV picture format with large search range.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128887581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 1.0 ns 64-bits GaAs adder using quad tree algorithm 采用四叉树算法的1.0 ns 64位砷化镓加法器
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497587
P. Royannez, A. Amara
{"title":"A 1.0 ns 64-bits GaAs adder using quad tree algorithm","authors":"P. Royannez, A. Amara","doi":"10.1109/GLSV.1996.497587","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497587","url":null,"abstract":"This paper describes a full custom 64-bits adder targeting the VITESSE E/D MESFET process HGaAsIII. This adder which respects a bit slice topology is part of the project of GaAs data-path compiler for ALLIANCE CAD TOOLs. GaAs's specific properties have been exploited in a full custom approach. Original architecture have been used to increase the parallelism of carries' computation. The layout is portable using a symbolic approach and could also be used with other E/D MESFET process.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122736985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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