A 1.0 ns 64-bits GaAs adder using quad tree algorithm

Abstract

This paper describes a full custom 64-bits adder targeting the VITESSE E/D MESFET process HGaAsIII. This adder which respects a bit slice topology is part of the project of GaAs data-path compiler for ALLIANCE CAD TOOLs. GaAs's specific properties have been exploited in a full custom approach. Original architecture have been used to increase the parallelism of carries' computation. The layout is portable using a symbolic approach and could also be used with other E/D MESFET process.