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Proceedings of the Sixth Great Lakes Symposium on VLSI最新文献

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Least upper bounds on the sizes of symmetric variable order based OBDDs 基于对称变序obdd大小的最小上界
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497607
Laura Heinrich-Litan, P. Molitor, Dirk Möller
{"title":"Least upper bounds on the sizes of symmetric variable order based OBDDs","authors":"Laura Heinrich-Litan, P. Molitor, Dirk Möller","doi":"10.1109/GLSV.1996.497607","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497607","url":null,"abstract":"This paper investigates the sizes of symmetric variable order based reduced binary decision diagrams for partially symmetric Boolean functions. It gives exact bounds for the maximum number of nonterminal vertices for the cases that the set of symmetric variables is treated as block which is located either at the front or at the back of the variable order.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117164931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A high speed VLSI architecture for scaleable ATM switches 用于可扩展ATM交换机的高速VLSI架构
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497596
P. Shipley, S. Sayed, M. Bayoumi
{"title":"A high speed VLSI architecture for scaleable ATM switches","authors":"P. Shipley, S. Sayed, M. Bayoumi","doi":"10.1109/GLSV.1996.497596","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497596","url":null,"abstract":"This paper presents a prototype of a VLSI chip to be used as a building block for an efficiently scaleable ATM switch with a link speed of 622.2 Mb/s. The chip is a 4/spl times/4 shared multibuffer ATM switch based on the distributing banyan architecture. It is efficient in storage space like a shared memory switch and scaleable in size like a space division switch. Since the architecture is self-routing, the chip contains all necessary routing control. Special high speed and low power circuitry is used. The chip is implemented in 1.0 micron static CMOS and measures only 25 mm/sup 2/ in area.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115160536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Exact computation of the entropy of a logic circuit 逻辑电路熵的精确计算
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497613
E. Macii, M. Poncino
{"title":"Exact computation of the entropy of a logic circuit","authors":"E. Macii, M. Poncino","doi":"10.1109/GLSV.1996.497613","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497613","url":null,"abstract":"Computing the entropy of a digital circuit has proved to be very useful for several applications in the area of VLSI system design. Recently, a method for entropy calculation has been used in the context of power estimation for logic circuits described at the register-transfer level. The technique has shown to be reasonably effective concerning the trade-off between the accuracy of the estimates produced and the execution time. However, the assumptions required to make the computation feasible are such that the obtained results are approximate. In this paper, we propose a symbolic algorithm for the exact calculation of the entropy of a logic circuit which is able to handle reasonably large examples without introducing any approximation. We present experimental data on standard benchmark designs in order to show the effectiveness of the new method; in addition, we compare our results to the ones obtained with the approximate approach. As a result, we observe a marginal penalty in the performance of the symbolic procedure; on the other hand, accuracy in the calculation increases significantly.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128770147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Software fault tolerance using dynamically reconfigurable FPGAs 使用动态可重构fpga的软件容错
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497590
K. Kwiat, W. Debany, S. Hariri
{"title":"Software fault tolerance using dynamically reconfigurable FPGAs","authors":"K. Kwiat, W. Debany, S. Hariri","doi":"10.1109/GLSV.1996.497590","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497590","url":null,"abstract":"An emerging class of Field-Programmable Gate Arrays (FPGAs) permits partial reconfiguration of the device without disturbing the rest of the array-even while the device is operating. Dynamic device reconfiguration allows novel approaches to the migration of algorithms from software to hardware. New simulation tools are required in order to fully exploit the FPGA's versatility. We demonstrate how FPGA cells can be programmed and reprogrammed to provide a virtual FPGA that is much larger than the physical FPGA. In the context of dependable computing, our FPGA-based approach shows promise of significant performance gains over traditional software-intensive approaches. We apply this capability to the enhancement of software fault tolerance.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131455319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Some issues in gray code addressing 灰色代码寻址中的一些问题
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497616
H. Mehta, R. Owens, M. J. Irwin
{"title":"Some issues in gray code addressing","authors":"H. Mehta, R. Owens, M. J. Irwin","doi":"10.1109/GLSV.1996.497616","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497616","url":null,"abstract":"Gray code addressing is one of the techniques previously proposed to reduce switching activity on high capacitance address bus lines. However in order to convert a system to gray address encoding there are several issues a designer needs to consider. This paper analyzes two issues which include gray code encodings for counter increments other than one and tradeoffs in power consumption incurred due to code conversions (binary to gray, gray to binary) when considering address increments and adders. Results are shown for different encodings and different configurations.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133887120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 110
A parametrical architecture for Reed-Solomon decoders Reed-Solomon解码器的参数化结构
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497598
Mariana-Eugenia Petre, G. Masera
{"title":"A parametrical architecture for Reed-Solomon decoders","authors":"Mariana-Eugenia Petre, G. Masera","doi":"10.1109/GLSV.1996.497598","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497598","url":null,"abstract":"Reed-Solomon decoders are digital decoders that use RS detecting and correcting of errors codes. RS codes are widely diffused in the transmission and storage of digital information and they are often used in concatenated encoding schemes to obtain great correction capabilities and good robustness to burst errors. In this study, a parametrical approach was chosen for decoder implementation at gate-level, based on the Berlekamp algorithm. This means that the decoder structure depends on two parameters: the bit number used for the symbol representation (m), and the error correction capability (t). The obtained architecture is suitable for a large number of different application (including high definition digital TV) and can be quickly synthesised using Synopsys for any required values of m and t.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115047472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A new faster algorithm for iterative placement improvement 一种新的快速迭代优化算法
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497591
Moazzem Hossain, B. Thumma, S. Ashtaputre
{"title":"A new faster algorithm for iterative placement improvement","authors":"Moazzem Hossain, B. Thumma, S. Ashtaputre","doi":"10.1109/GLSV.1996.497591","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497591","url":null,"abstract":"We present a new faster design-style independent iterative placement improvement algorithm. Randomized simulated annealing based algorithms produce good result. But on very large designs, the inherently long run-time makes it prohibitive to use randomized algorithm. On the other hand deterministic improvement methods do not produce as good a result as the simulated annealing based algorithms. Moreover, none of the existing placement improvement techniques addresses the non row-based design style. In this paper, we combine the advantages of both the random and deterministic approach to develop a new faster placement improvement algorithm. Experimental results show that our algorithm performs much better than existing placement improvement algorithm. On some benchmarks, our algorithm is as much as 8/spl times/ faster than that on Domino with a significant reduction in total net length.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115435729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A minimum-area floorplanning algorithm for MBC designs MBC设计的最小面积平面规划算法
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497593
D. Mehta, N. Sherwani
{"title":"A minimum-area floorplanning algorithm for MBC designs","authors":"D. Mehta, N. Sherwani","doi":"10.1109/GLSV.1996.497593","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497593","url":null,"abstract":"This paper identifies important objectives that an MBC floorplanner using flexible, arbitrary rectilinear shapes for standard cell regions should achieve including area minimization, proximity, and connectivity. It then presents an algorithm that guarantees area minimization and connectivity and gives good results with respect to proximity.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128300811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Boolean function representation using parallel-access diagrams 使用并行访问图的布尔函数表示
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497604
V. Bertacco, M. Damiani
{"title":"Boolean function representation using parallel-access diagrams","authors":"V. Bertacco, M. Damiani","doi":"10.1109/GLSV.1996.497604","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497604","url":null,"abstract":"In this paper we introduce a nondeterministic counterpart to Reduced, Ordered Binary Decision Diagrams for the representation and manipulation of logic functions. ROBDDs are conceptually related to deterministic finite automata (DFA), accepting the language formed by the minterms of a function. This analogy suggests the use of nondeterministic devices as language recognizers. Unlike ROBDDs, the diagrams introduced in this paper allow multiple outgoing edges with the same label. By suitably restricting the degree of nondeterminism, we still obtain a canonical form for logic functions. Using PADs, we are able to reduce the memory occupation with respect to traditional ROBDDs for several benchmark functions. Moreover the analysis of the PAD graphs allowed us to sometimes identify new and better variable ordering for several benchmark circuits.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131584214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A design exploration environment 设计探索环境
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497597
J. Wilberg, A. Kuth, R. Camposano, W. Rosenstiel, H. Vierhaus
{"title":"A design exploration environment","authors":"J. Wilberg, A. Kuth, R. Camposano, W. Rosenstiel, H. Vierhaus","doi":"10.1109/GLSV.1996.497597","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497597","url":null,"abstract":"The paper describes the design exploration environment of the CASTLE system. The environment allows the exploration of hardware and software for complex processor designs. The exploration is subdivided into the measurement phase and the analysis phase. The measurement phase uses a retargetable compiler to determine the performance for a large number of different processors and different programs. These fine-grained data form the input of the analysis phase. It transforms the data into abstract representations that are visualized for the designer. The results are integrated into an HTML-based framework.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115957803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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