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Proceedings of the Sixth Great Lakes Symposium on VLSI最新文献

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Test generation for networks of interacting FSMs using symbolic techniques 使用符号技术生成交互fsm网络的测试
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497621
Fabrizio Ferrandi, F. Fummi, E. Macii, M. Poncino, D. Sciuto
{"title":"Test generation for networks of interacting FSMs using symbolic techniques","authors":"Fabrizio Ferrandi, F. Fummi, E. Macii, M. Poncino, D. Sciuto","doi":"10.1109/GLSV.1996.497621","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497621","url":null,"abstract":"This paper presents a new testing strategy for networks of interacting FSMs. The approach allows us to generate test patterns for faults in the network by separately handling the network's components. The proposed algorithms are fully symbolic; therefore, they allow the manipulation of large designs. Experimental results, though preliminary, are promising.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114430751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Loop-list scheduling for heterogeneous functional units 异构功能单元的循环表调度
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497583
Yun-Nan Chang, Ching-Yi Wang, K. Parhi
{"title":"Loop-list scheduling for heterogeneous functional units","authors":"Yun-Nan Chang, Ching-Yi Wang, K. Parhi","doi":"10.1109/GLSV.1996.497583","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497583","url":null,"abstract":"This paper presents a new heuristic, concurrent, iterative loop-based scheduling and allocation algorithm for high-level synthesis of digital signal processing (DSP) architectures using heterogeneous functional units. In a heterogeneous architecture, functional units could be either bit-serial or digit-serial or bit-parallel. We assume a library of heterogeneous implementation style based functional units is available. Experiments show that this new heuristic synthesis approach generates optimal and near-optimal area solutions. Although optimum synthesis of such architectures were proposed recently using an integer linear programming (ILP) model, our method can produce similar solutions in one to two orders of magnitude less time, at the expense of sacrificing the cost optimality. We compare the solutions generated by the proposed algorithm with the optimal solutions generated by the ILP approach and other recent techniques. We have incorporated this new algorithm into the Minnesota ARchitecture Synthesis (MARS-II) system.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128053410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
An optimal ILP formulation for minimizing the number of feedthrough cells in standard cell placement 一个最佳的ILP配方，以减少在标准细胞放置的馈通细胞的数量
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497602
Jin-Tai Yan
{"title":"An optimal ILP formulation for minimizing the number of feedthrough cells in standard cell placement","authors":"Jin-Tai Yan","doi":"10.1109/GLSV.1996.497602","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497602","url":null,"abstract":"Standard cell design style has been widely applied for the design automation of VLSI circuits because of the easy implementation of the layout design. Since the aim of most of standard cell design systems is to minimize the utilization of chip area, the number of feedthrough cells in a standard cell layout will be further minimized to reduce the layout site. In this paper, first, we model a row assignment problem to minimize the number of feedthrough cells in a standard cell placement. Furthermore, an integer linear programming (ILP) optimal approach is proposed to minimize the number of feedthrough cells for the row assignment in a standard cell placement. Finally, two standard cell benchmarks, Primary1 and Primary2, have been tested on the proposed ILP approach for the assignment of different number of rows, and the experimental results show that the ILP approach is efficient for the assignment of cell rows.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133263673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A new model for general connectivity and its application to placement 一般连通性的新模型及其在布局中的应用
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497594
Jianjian Song, Heng Kek Choo, W. Zhuang
{"title":"A new model for general connectivity and its application to placement","authors":"Jianjian Song, Heng Kek Choo, W. Zhuang","doi":"10.1109/GLSV.1996.497594","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497594","url":null,"abstract":"A new model for general connectivity is defined and its application to placement is presented in this paper. The new model is based on better understanding and analysis of connection graphs. Its computation time in the worst case is O(N/sup k+2/), where N is the number of cells in a connection graph and k is the order of general connectivity. 41 placements for three circuits were carried out with our new model and the results are compared with those from the conductance model proposed by an earlier paper. Our new model is better than the conductance model because ours characterizes the connection graph more accurately, is faster to compute, and produces better results. The best performance improvements for the three circuits are 35.4% (HK5601), 37.8%(HK5852), and 19.2%(HK5851).","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"353 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115923212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Improving circuit testability by clock control 通过时钟控制提高电路的可测试性
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497635
K. L. Einspahr, S. Seth, V. Agrawal
{"title":"Improving circuit testability by clock control","authors":"K. L. Einspahr, S. Seth, V. Agrawal","doi":"10.1109/GLSV.1996.497635","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497635","url":null,"abstract":"The testability of a sequential circuit can be improved by controlling the clock of individual storage elements during testing. We propose several clock control strategies derived from an analysis of the circuit, its S-graph structure, and its function. Through examples we show how the number of clocks affects the circuit's testability. It is shown that if certain flip-flops (FFs) are scanned (or otherwise initialized), the remaining FFs can be controlled and initialized to any arbitrary state using the clock control. We derive a controllability graph and use it to assign clocks to FFs and to schedule the clocks to set the FFs to an arbitrary state during test. Our analysis of sequential benchmark circuits indicates that this could be an attractive scheme for combining partial scan with clock control.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121563028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A VLSI interconnection network router using a D-CAM with hidden refresh 一个使用隐藏刷新的D-CAM的VLSI互连网络路由器
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497627
J. Delgado-Frías, J. Nyathi, Chester L. Miller, D. Summerville
{"title":"A VLSI interconnection network router using a D-CAM with hidden refresh","authors":"J. Delgado-Frías, J. Nyathi, Chester L. Miller, D. Summerville","doi":"10.1109/GLSV.1996.497627","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497627","url":null,"abstract":"A VLSI implementation of a programmable router scheme for parallel interconnection network architectures is presented in this paper. The router executes routing algorithms in 1.5 clock cycles, this being the fastest approach for flexible routers. To further increase throughput, the router operation has been made pipelined, achieving 1 routing decision per cycle. The implementation is based on a content addressable memory (CAM) that supports per entry unique bit masking. This programmable CAM requires few entries; this in turn makes it possible to implement a dynamic approach in order to reduce the transistor count. We have provided circuitry and arranged timing to achieve refreshing of the stored data in a hidden fashion. In addition to the CAM, we have incorporated a fast priority scheme that allows only one entry to be selected and a memory that stores the port assignment. The number of required CAM entries is extremely small; it is of the same order as the output ports.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122314407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Rapid prototyping for fuzzy systems 模糊系统的快速原型设计
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497625
C. Phongpensri, S. Tongsima, E. Sha
{"title":"Rapid prototyping for fuzzy systems","authors":"C. Phongpensri, S. Tongsima, E. Sha","doi":"10.1109/GLSV.1996.497625","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497625","url":null,"abstract":"One of the common problems for fuzzy system implementation arises from the complications of the fuzzy inference process. Extra computations are required to deduce a consequence due to nature of fuzzy sets. Furthermore, considerable simulations need to be performed to verify system functions. In order to reduce the prototyping time, the fuzzy system is partitioned into hardware and software portions. The model, called Fuzzy Rule-based Automata (FRA), is proposed to simplify fuzzy rule base. Since most rule base are rarely changed, they can be implemented in hardware to speedup the running time. Special computations for inference process is taken care by software to reduce hardware complications which yields prototype flexibility.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116879422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
On locally optimal breaking of complex cyclic vertical constraints in VLSI channel routing VLSI通道路由中复杂循环垂直约束的局部最优打破
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497600
A. D. Johnson
{"title":"On locally optimal breaking of complex cyclic vertical constraints in VLSI channel routing","authors":"A. D. Johnson","doi":"10.1109/GLSV.1996.497600","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497600","url":null,"abstract":"Existing theory has supported deterministic polynomial time procedures for locally optimal breaking (LOB) of two classes of directed circuits (DC) in the vertical constraint graph, the classes of vertex disjoint DCs, and of couples of connected DCs. New LOB theory is reported that supports procedures for LOB of any number of DCs sharing a common vertex, or a common path, and of DCs in uniform ladder VCGs. A significant aspect of the new theory is that it relies on procedures for couples of connected DCs as tools for breaking more complex structures of connected DCs. Application of the theory in genetic channel routers is reported elsewhere.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115984339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Input pattern classification for transistor level testing of bridging faults in BiCMOS circuits BiCMOS电路中桥接故障晶体管电平测试的输入模式分类
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497622
S. Menon, A. Jayasumana, Y. Malaiya
{"title":"Input pattern classification for transistor level testing of bridging faults in BiCMOS circuits","authors":"S. Menon, A. Jayasumana, Y. Malaiya","doi":"10.1109/GLSV.1996.497622","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497622","url":null,"abstract":"Combining the advantages of bipolar and CMOS, BiCMOS is emerging as a major technology for high speed, high performance, digital and mixed signal applications. Recent investigations have revealed that bridging faults can be a major failure mode in ICs. This paper presents the effects of bridging faults affecting p- or n-parts and input bridging faults of logical nodes affecting p- and n-parts. It is shown that bridging faults can be detected by I/sub DDQ/ monitoring in BiCMOS devices. An input pattern classification scheme is presented for bridging faults. These classes of input patterns are then used to obtain test sets for bridging fault detection.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"12 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116929690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Transistor chaining in CMOS leaf cells of planar topology 平面拓扑CMOS叶单元的晶体管链化
Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI: 10.1109/GLSV.1996.497619
B. Carlson, C. Y. Chen, D. Meliksetian
{"title":"Transistor chaining in CMOS leaf cells of planar topology","authors":"B. Carlson, C. Y. Chen, D. Meliksetian","doi":"10.1109/GLSV.1996.497619","DOIUrl":"https://doi.org/10.1109/GLSV.1996.497619","url":null,"abstract":"A technique for chaining the transistors in the layouts of static CMOS leaf cells is presented and analyzed. This new method is superior to existing techniques, since it can operate on a more general class of circuits and is very efficient. It is shown that the layout width of a CMOS leaf cell can be significantly reduced (nearly 40% in the average case) by transistor chaining. Moreover, more than half of the switching functions of four variables have optimal CMOS circuit implementations with non-series/parallel topologies. Therefore, the use of non-series/parallel circuits can have a positive global impact on layout area and performance. The transistor chaining technique presented in this paper produces the optimal solution for 82% of the circuits tested, and has linear time complexity.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125756681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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