Input pattern classification for transistor level testing of bridging faults in BiCMOS circuits

Abstract

Combining the advantages of bipolar and CMOS, BiCMOS is emerging as a major technology for high speed, high performance, digital and mixed signal applications. Recent investigations have revealed that bridging faults can be a major failure mode in ICs. This paper presents the effects of bridging faults affecting p- or n-parts and input bridging faults of logical nodes affecting p- and n-parts. It is shown that bridging faults can be detected by I/sub DDQ/ monitoring in BiCMOS devices. An input pattern classification scheme is presented for bridging faults. These classes of input patterns are then used to obtain test sets for bridging fault detection.