Timing and power optimization by gate sizing considering false path

Abstract

This paper introduces a new gate sizing approach for area and power optimization considering path sensitization. The approach selects a set of long paths from a combinational circuit by means of a performance optimization oriented heuristic path selection approach. The longest sensitizable path delay of the circuit can be restricted within the specified delay limit if we set the specified delay limit on these paths in an LP based iterative gate sizing process. Since the approach get rid of unnecessary delay constraints on long false paths, results with smaller circuit area or power dissipation is expected. Experiments on benchmark circuits show that the proposed approach can substantially reduce the circuit area and power dissipation by considering path sensitization for some false path dominated circuits.