{"title":"采用四叉树算法的1.0 ns 64位砷化镓加法器","authors":"P. Royannez, A. Amara","doi":"10.1109/GLSV.1996.497587","DOIUrl":null,"url":null,"abstract":"This paper describes a full custom 64-bits adder targeting the VITESSE E/D MESFET process HGaAsIII. This adder which respects a bit slice topology is part of the project of GaAs data-path compiler for ALLIANCE CAD TOOLs. GaAs's specific properties have been exploited in a full custom approach. Original architecture have been used to increase the parallelism of carries' computation. The layout is portable using a symbolic approach and could also be used with other E/D MESFET process.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"55 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A 1.0 ns 64-bits GaAs adder using quad tree algorithm\",\"authors\":\"P. Royannez, A. Amara\",\"doi\":\"10.1109/GLSV.1996.497587\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes a full custom 64-bits adder targeting the VITESSE E/D MESFET process HGaAsIII. This adder which respects a bit slice topology is part of the project of GaAs data-path compiler for ALLIANCE CAD TOOLs. GaAs's specific properties have been exploited in a full custom approach. Original architecture have been used to increase the parallelism of carries' computation. The layout is portable using a symbolic approach and could also be used with other E/D MESFET process.\",\"PeriodicalId\":191171,\"journal\":{\"name\":\"Proceedings of the Sixth Great Lakes Symposium on VLSI\",\"volume\":\"55 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-03-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the Sixth Great Lakes Symposium on VLSI\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/GLSV.1996.497587\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the Sixth Great Lakes Symposium on VLSI","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GLSV.1996.497587","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 1.0 ns 64-bits GaAs adder using quad tree algorithm
This paper describes a full custom 64-bits adder targeting the VITESSE E/D MESFET process HGaAsIII. This adder which respects a bit slice topology is part of the project of GaAs data-path compiler for ALLIANCE CAD TOOLs. GaAs's specific properties have been exploited in a full custom approach. Original architecture have been used to increase the parallelism of carries' computation. The layout is portable using a symbolic approach and could also be used with other E/D MESFET process.
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