A CMOS VLSI implementation of an N/spl times/N multiplexing circuitry for ATM applications

A non internal blocking ATM packet switching network using CMOS technology has been developed for an N/spl times/N switch. A multiplexing circuitry with 32 inputs was designed and implemented using simple logic gates. The development has utilized an interconnection network of 1/spl times/32 parallel expander circuits. The control unit consisting of serial shift registers and latches to keep the destination path open for the length of the packet, were designed using MAGIC software and simulated by IRSIM. As low as 5 ns delay was estimated by the 1/spl times/32 expander circuit, while the clock generated by the combinational circuit for latching showed a delay of 190 ns. The system has been fabricated using MOSIS services, and as minimum of 5 ns delay was measured between the input and output nodes of the switching circuit.