A parameterized index-generator for the multi-dimensional interleaving optimization

Abstract

The novel optimization technique for the design of application specific integrated circuits of multi-dimensional problems, called multi-dimensional interleaving consists of an expansion and compression of the iteration space. It guarantees that all functional elements of a circuitry can be executed simultaneously, and no additional memory queues proportional to the problem size are required. Such technique, that considers the parallelism inherent to multi-dimensional problems, depend on loop transformations that require a new execution sequence of the loop. This study presents a new approach on synthesizing multidimensional (nested) loops, where pre-processor tools can rewrite the instructions in such a way to accommodate the required changes in the optimized design. This new approach is expected to improve the design cycle by including multidimensional signal processing and other common applications in the scope of the synthesis tools.