Performance-driven interconnect global routing

Abstract

In this paper, we propose a global routing algorithm for multi-layer building-block layouts. The algorithm is based on successive rip up and rerouting while satisfying edge capacity constraints as well as achieving higher routability and good routing flexibility. The initial solution consists of nets routed independently by the SERT-C algorithm which minimizes the Elmore delay at critical sink of a Steiner tree. Then, all the nets with the most congested edge, i.e., the edge with maximum flow, are ripped up and rerouted by using an iterative hierarchical approach. For each iteration, a window is specified according to the span of the ripped-up nets or an upper bound if the span is too large. Rerouting is done hierarchically within the window by using integer programming to optimize the flow uniformity. The algorithm terminates when the flow uniformity can not be further improved. The algorithm has been implemented and interfaced with a placement tool. Experiments show that the algorithm can improve the flow uniformity by 19% to 97%. The final results include the number of routing layers needed to complete the routing. Thus, the method is also useful in determining the required number of layers for pack aging design using multi-chip models.