基于fpga的高性能页面布局分割

Proceedings of the Sixth Great Lakes Symposium on VLSI Pub Date : 1996-03-22 DOI:10.1109/GLSV.1996.497588

N. Ratha, Anil K. Jain, D. Rover

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引用次数: 4

摘要

提出了一种定位文本、背景和半色调区域的页面布局分割算法。该算法已在基于fpga的阵列处理器Splash 2上实现。由赛灵思合成工具确定的速度预计应用速度为5 MHz。对于大小为1,024/spl times/1,024像素的文档，与SparcStation 20相比，已经实现了两个数量级的显著加速。

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FPGA-based high performance page layout segmentation

A page layout segmentation algorithm for locating text, background and halftone areas is presented. The algorithm has been implemented on Splash 2-an FPGA-based array processor. The speed as determined by the Xilinx synthesis tools projects an application speed of 5 MHz. For documents of size 1,024/spl times/1,024 pixels, a significant speedup of two orders of magnitude compared to a SparcStation 20 has been achieved.

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Proceedings of the Sixth Great Lakes Symposium on VLSI

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