{"title":"一个3 V-50 MHz模拟CMOS电流模式高频滤波器与负电阻负载","authors":"J. Hyun, K. Yoon","doi":"10.1109/GLSV.1996.497630","DOIUrl":null,"url":null,"abstract":"A low voltage analog CMOS current-mode continuous-time high frequency filter with a negative resistance load (NRL) is proposed. To design a current integrator, we use a modified simple current mirror with a NRL to increase the output resistance. The current integrator is designed to have the frequency behavior enhancement and operate in low voltage by employing a simple mirror structure and diode connected input transistor. The third order Butterworth low pass filter using a current integrator is synthesized and simulated with a 1.5 /spl mu/m n-well process. Simulation result shows cutoff frequency of 50 MHz and power consumption of 2.4 mW/pole with a 3 V power supply.","PeriodicalId":191171,"journal":{"name":"Proceedings of the Sixth Great Lakes Symposium on VLSI","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A 3 V-50 MHz analog CMOS current-mode high frequency filter with a negative resistance load\",\"authors\":\"J. Hyun, K. Yoon\",\"doi\":\"10.1109/GLSV.1996.497630\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A low voltage analog CMOS current-mode continuous-time high frequency filter with a negative resistance load (NRL) is proposed. To design a current integrator, we use a modified simple current mirror with a NRL to increase the output resistance. The current integrator is designed to have the frequency behavior enhancement and operate in low voltage by employing a simple mirror structure and diode connected input transistor. The third order Butterworth low pass filter using a current integrator is synthesized and simulated with a 1.5 /spl mu/m n-well process. Simulation result shows cutoff frequency of 50 MHz and power consumption of 2.4 mW/pole with a 3 V power supply.\",\"PeriodicalId\":191171,\"journal\":{\"name\":\"Proceedings of the Sixth Great Lakes Symposium on VLSI\",\"volume\":\"14 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-03-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the Sixth Great Lakes Symposium on VLSI\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/GLSV.1996.497630\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the Sixth Great Lakes Symposium on VLSI","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GLSV.1996.497630","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 3 V-50 MHz analog CMOS current-mode high frequency filter with a negative resistance load
A low voltage analog CMOS current-mode continuous-time high frequency filter with a negative resistance load (NRL) is proposed. To design a current integrator, we use a modified simple current mirror with a NRL to increase the output resistance. The current integrator is designed to have the frequency behavior enhancement and operate in low voltage by employing a simple mirror structure and diode connected input transistor. The third order Butterworth low pass filter using a current integrator is synthesized and simulated with a 1.5 /spl mu/m n-well process. Simulation result shows cutoff frequency of 50 MHz and power consumption of 2.4 mW/pole with a 3 V power supply.
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