A high speed, real-to-quadrature converter with filtering and decimation

Abstract

The design of a high speed, real-to-quadrature converter chip set with filtering, decimation, built-in self-test (BIST), and IEEE 1149.1 based boundary scan will be presented. The 15,000 gate application specific integrated circuit (ASIC) implemented in 1.5 /spl mu/m CMOS gate array technology has 3 half-band filters with 3, 7, and 11 taps which can be cascaded in a number of combinations. The intended ASIC application is the processing of narrowband radio signals at IF frequencies. The paper addresses the ASIC's functionality, VLSI implementation and test methodology, and provides both simulation and test data.