A 3 V-50 MHz analog CMOS current-mode high frequency filter with a negative resistance load

J. Hyun, K. Yoon
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引用次数: 1

Abstract

A low voltage analog CMOS current-mode continuous-time high frequency filter with a negative resistance load (NRL) is proposed. To design a current integrator, we use a modified simple current mirror with a NRL to increase the output resistance. The current integrator is designed to have the frequency behavior enhancement and operate in low voltage by employing a simple mirror structure and diode connected input transistor. The third order Butterworth low pass filter using a current integrator is synthesized and simulated with a 1.5 /spl mu/m n-well process. Simulation result shows cutoff frequency of 50 MHz and power consumption of 2.4 mW/pole with a 3 V power supply.
一个3 V-50 MHz模拟CMOS电流模式高频滤波器与负电阻负载
提出了一种具有负电阻负载的低电压模拟CMOS电流型连续高频滤波器。为了设计一个电流积分器,我们使用了一个带有NRL的改进的简单电流镜来增加输出电阻。电流积分器采用简单的镜面结构和二极管连接的输入晶体管,具有频率特性增强和低电压工作。利用电流积分器合成了三阶巴特沃斯低通滤波器,并以1.5 /spl mu/m的n阱过程进行了仿真。仿真结果表明,在3v电源下,截止频率为50 MHz,功耗为2.4 mW/极。
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